adjust1_mult.vhd

数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.

 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.equ_pak.all;

entity adjust1_mult is
          port(
            clk:in std_logic;
             resetn:in std_logic:='1';
             xin:in data1_array(2 downto 0);
           f_zn:in std_logic_vector(8 downto 0);
           cmp1_en:in std_logic:='0';
           mult_en:in std_logic:='0';
           cmp2_en:in std_logic:='0';
           addrgene_en:in std_logic:='0';
           w_addr:out std_logic_vector(2 downto 0);
           data:out std_logic_vector(15 downto 0);
           ram_ch:out std_logic
        );
   end adjust1_mult;
  
   architecture rtl of adjust1_mult is
        signal cmp_xin:data1_array(2 downto 0);
        signal cmp_f_zn:std_logic_vector(8 downto 0);
        signal temp1_data:coef_array(2 downto 0);
        signal temp2_data:coef_array(2 downto 0);
        signal temp2_datam:coef_array(2 downto 0);
        signal data_m1: std_logic_vector(15 downto 0);
        signal w_addr_m1: std_logic_vector(2 downto 0);
        signal address:std_logic_vector(2 downto 0);
        signal addrgene_en_m:std_logic;
  begin
xin_cmp1:for i in 2 downto 0 generate
        p:cmplcode2 generic map(n=>12)
             port map(clk,resetn,cmp1_en,xin(i),cmp_xin(i));           
           end generate;

f_zn_cmp1:cmplcode2 generic map(n=>9)
             port map(clk,resetn,cmp1_en,f_zn,cmp_f_zn);


  um:for i in 2 downto 0 generate
     mul : mult2
     port map(clk,resetn,cmp_f_zn,cmp_xin(i),mult_en,temp1_data(i));
     end generate;

x:for i in 2 downto 0 generate
       pui:cmplcode2 generic map(n=>16)
          port map(clk, resetn, cmp2_en,temp1_data(i),temp2_datam(i));
end generate;

   
   process(clk,resetn)
         variable count:std_logic_vector(2 downto 0);
begin 
           if resetn='0' then
              count:=(others=>'0');
              addrgene_en_m<='0';
           elsif clk'event and clk='1' then
              addrgene_en_m<=addrgene_en;
               if addrgene_en_m='1' then
                     if count<7 then 
                          count:=count+1;
                      else
                          count:=(others=>'0');
                     end if;
                 end if;
                end if;
             address<=count;
          end process;
 
       process(clk,address)
             variable m1:std_logic_vector(16 downto 0);
             variable m2:std_logic_vector(16 downto 0);
             variable m3:std_logic_vector(16 downto 0);
             variable m4:std_logic_vector(16 downto 0);
             variable m:std_logic_vector(15 downto 0);
   
     begin
             if clk'event and clk='1' then
                temp2_data<=temp2_datam;
               case address is
                      when "000"=>m:=(others=>'0');
                      when "001"=>m:=temp2_data(2);
                      when "010"=>m:= temp2_data(1);
                      when "011"=>m1:='0'&temp2_data(2)+temp2_data(1);
                                  m:=m1(16 downto 1);
                      when "100"=>m:= temp2_data(0);
                      when "101"=>m2:='0'&temp2_data(2)+temp2_data(0);
                                  m:=m2(16 downto 1);
                      when "110"=>m3:='0'&temp2_data(1)+temp2_data(0);
                                  m:=m3(16 downto 1);
                      when "111"=>m3:='0'&temp2_data(1)+temp2_data(0);
                                  m4:= '0'&temp2_data(2)+m3(16 downto 1);
                                  m:=m4(16 downto 1);
                      when others=>null;
               end case;
            end if;
                 data_m1<=m;
                  w_addr_m1<=address;
          end process;
      
      process(clk,resetn)
         begin
                if resetn='0' then
                        data<=(others=>'0');
                         w_addr<=(others=>'0');
                         ram_ch<='0';
                elsif clk'event and clk='1' then
                         data<=data_m1;
                         w_addr<=w_addr_m1;
                         ram_ch<='1';
                   end if;
             end process;
end rtl;