shift.vhdl

来自「Direct Digital Synthesis (DDS),最好用的可步进的数」· VHDL 代码 · 共 30 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity shift is
		port(data :in std_logic;
			  upclk: in std_logic;
			  reset:in std_logic;
			  dataout:out std_logic_vector(15 downto 0));
end shift;

architecture Behavioral of shift is
	--signal cnt:integer range 0 to 15;
	signal dtemp:std_logic_vector(15 downto 0):=(others=>'0');
begin
   process(upclk,reset)	--每次有16个upclk
	begin
	  	if reset='1' then dtemp<=(others=>'0');
		elsif upclk'event and upclk='1' then 
		 dtemp<=data&dtemp(15 downto 1);			  
	   end if;		 
	end process;
   dataout<=dtemp;
end Behavioral;