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--regne.vhd n-bit register with enable library ieee ; use ieee.std_logic_1164.all ; entity regne is generic ( n : integer := 12 ) ; port ( r : in std_logic_vector(n-1 downto 0) ;--register

--negative.vhd correct negative number circuit library ieee ; use ieee.std_logic_1164.all; use work.components.all; entity negative is port( a : in std_logic_vector(11 downto 0);--块

--bcdadd.vhd 1 digit bcd adder library ieee ; use ieee.std_logic_1164.all; use work.components.all; entity bcdadd is port( a : in std_logic_vector(3 downto 0);--砆

--bcd.vhd 1 digits bcd adder/subtractor library ieee ; use ieee.std_logic_1164.all; use work.components.all; entity bcd is port( a : in std_logic_vector(3 downto 0);--砆

--multiplier.vhd n-bit multiplier library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all ; use work.components.all ; entity multiplier is generic ( n : integer := 7; nn :

--bcd3.vhd 3 digits bcd adder/subtractor library ieee ; use ieee.std_logic_1164.all; use work.components.all; entity bcd3 is port( a : in std_logic_vector(11 downto 0);--砆

library ieee;--锁存器 use ieee.std_logic_1164.all; entity reg32b is port(load: in std_logic; din: in std_logic_vector(15 downto 0); dout: out std_logic_vector(15 downto 0)); end e

library ieee;--十进制计数器 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt10 is port(clk: in std_logic;--时钟信号 clr: in std_logic;--清零信号 ena: in std_logic;--使能信

library ieee; use ieee.std_logic_1164.all; entity REG26B is port(CLK:in std_logic; DIN:in std_logic_vector(29 downto 0); DOUT:out std_logic_vector(29 downto 0)); end; architecture

library ieee; use ieee.std_logic_1164.all; entity mzh is port(m5:out std_logic_vector(2 downto 0)); end; architecture one of mzh is begin m5