reg32b.vhd

基于VHDL语言的频率计具有高速计频

library ieee;--锁存器
use ieee.std_logic_1164.all;
entity reg32b is
  port(load: in std_logic;
        din: in std_logic_vector(15 downto 0);
        dout: out std_logic_vector(15 downto 0));
end entity reg32b;
architecture be of reg32b is
begin
process(load,din)
begin
if load'event and load='1' then
 dout<=din;
end if;
end process;
end architecture be;