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Logic Analyzer 的代码
ldenaddsub.vhd
--
-- This is an adder-subtractor VHDL module.
-- The module is a parallel loadable, synchronous
-- set/reset, clock enabled adder-subtractor.
-- this code implements a simple and compact
-- add
clk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk is
port(
clk : in std_logic;
address : out std_logic_vector(5 downto 0));
end clk;
a
fulladder_4.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FullAdder_4 IS
PORT(dataA,dataB:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
carryin:IN STD_LOGIC;
sum:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
carryout:OUT S
clkdiv_2p5.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ClkDiv_2p5 IS
PORT(clk:IN STD_LOGIC;
clkdiv2p5:OUT STD_LOGIC);
END ENTITY ClkD
数控分频器的设计.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PULSE IS
PORT ( CLK : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FO
lu20040094.vhd
LIBRARY altera;
LIBRARY IEEE;
USE altera.maxplus2.ALL;
USE IEEE.std_logic_1164.ALL;
ENTITY LU20040094 IS
PORT ( s: in STD_LOGIC_VECTOR (15 DOWNTO 0);
m: in STD_LOGIC_VECTOR
numlatch.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Numlatch is
port
(clock,en:in std_logic;
numina:in std_logic_vector(3 downto 0);
numinb:in std_logic_vecto
data_pro.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity data_pro is
port
( clk:in std_logic;
enable:in std_logic;
Numf1,Numf2,Numf3:in std_logic_vector(3 downto
baseclk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity baseclk is
port
( clk1M,clk100k:in std_logic;
period:in std_logic;
clk:out std_logic
);
end;
archit
clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk:in std_logic;
reset:in std_logic;
dins:in s