data_pro.vhd

本频率计具有测周、测频、测量占空比等基本功能

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity data_pro is
port
( clk:in std_logic;
  enable:in std_logic;
  Numf1,Numf2,Numf3:in std_logic_vector(3 downto 0);
  beichu1,beichu2,beichu3:in std_logic_vector(3 downto 0);
  chu1,chu2,chu3:in std_logic_vector(3 downto 0);
  data:out std_logic_vector(7 downto 0)
 );
 end;
 
 architecture a of data_pro is
 signal d:std_logic_vector(7 downto 0);
 signal counter:Integer range 0 to 6;
 begin
  process(clk,enable)
      begin
         if(enable='0') then
             counter<=0;
           elsif (clk'event and clk='1') then
             if counter=6 then
               counter<=0;
              else counter<=counter+1;
              end if;
            end if;
          
   end process;
  process(counter)
      begin
         case counter is
          when 1=>d<=Numf2&Numf1;
          when 2=>d<="0000"&Numf3;
          when 3=>d<=beichu2&beichu1;
          when 4=>d<="0000"&beichu3;
          when 5=>d<=chu2&chu1;
          when 6=>d<="0000"&chu3;
          when others=>null;
          end case;
       end process;
      data<=d;
 end a;