lu20040094.vhd

组成原理实验作业用VHDL实现的六层电梯程序

LIBRARY altera;
LIBRARY IEEE;
USE altera.maxplus2.ALL;
USE IEEE.std_logic_1164.ALL;


ENTITY LU20040094 IS
       PORT (	s: in STD_LOGIC_VECTOR (15 DOWNTO 0);
		        m: in STD_LOGIC_VECTOR (3 DOWNTO 0);
		       ci: in STD_LOGIC;
		       an: in STD_LOGIC_VECTOR (15 DOWNTO 0);
		       bn: in STD_LOGIC_VECTOR (15 DOWNTO 0);
		       gn: out STD_LOGIC_VECTOR (3 DOWNTO 0);
		       pn: out STD_LOGIC_VECTOR (3 DOWNTO 0);
		       fn: out STD_LOGIC_VECTOR (15 DOWNTO 0);
		     aeqb: out STD_LOGIC_VECTOR (3 DOWNTO 0);
		      cn4: buffer STD_LOGIC;
              cn8: buffer STD_LOGIC;
             cn12: buffer STD_LOGIC;
             cn16: buffer STD_LOGIC);
END LU20040094;

ARCHITECTURE ADDER OF LU20040094 IS
	COMPONENT a_74181 
	PORT (	    s: in STD_LOGIC_VECTOR (3 downto 0);
		        m: in STD_LOGIC;
		       cn: in STD_LOGIC;
		      a3n: in STD_LOGIC;
		      a2n: in STD_LOGIC;
		      a1n: in STD_LOGIC;
		      a0n: in STD_LOGIC;
		      b3n: in STD_LOGIC;
		      b2n: in STD_LOGIC;
		      b1n: in STD_LOGIC;
		      b0n: in STD_LOGIC;
		       gn: out STD_LOGIC;
		       pn: out STD_LOGIC;
		      f3n: out STD_LOGIC;
		      f2n: out STD_LOGIC;
		      f1n: out STD_LOGIC;
		      f0n: out STD_LOGIC;
		     aeqb: out STD_LOGIC;
		      cn4: out STD_LOGIC);
    END COMPONENT;
   
    COMPONENT soft
	PORT (  A_IN:  in STD_LOGIC;
		    A_OUT: out STD_LOGIC);
    END COMPONENT;

    SIGNAL carry_tmp: std_logic_vector( 2 DOWNTO 0);
   
BEGIN
        adderx1: a_74181
        PORT MAP( s(3 DOWNTO 0), m(0), ci, 
                  an(3), an(2), an(1), an(0), 
                  bn(3), bn(2), bn(1), bn(0), 
                  gn(0), pn(0),
		          fn(3), fn(2), fn(1), fn(0),
		          aeqb(0),cn4);
        
		connection1: soft
        PORT MAP( cn4,carry_tmp(0));
		
		adderx2: a_74181
        PORT MAP( s(7 DOWNTO 4), m(1), carry_tmp(0), 
                  an(7), an(6), an(5), an(4), 
                  bn(7), bn(6), bn(5), bn(4), 
                  gn(1), pn(1),
		          fn(7), fn(6), fn(5), fn(4),
		          aeqb(1),cn8);
      

        connection2: soft
        PORT MAP(cn8, carry_tmp(1));

		
		
		
		adderx3: a_74181
		PORT MAP( s(11 DOWNTO 8),  m(2), carry_tmp(1), 
                  an(11), an(10), an(9), an(8), 
                  bn(11), bn(10), bn(9), bn(8), 
                  gn(2), pn(2),
		          fn(11), fn(10), fn(9), fn(8),
		          aeqb(2),cn12);


       connection3: soft
       PORT MAP( cn12, carry_tmp(2));

       adderx4: a_74181
	   PORT MAP( s(15 DOWNTO 12),  m(3), carry_tmp(2), 
                 an(15), an(14), an(13), an(12), 
                 bn(15), bn(14), bn(13), bn(12), 
                 gn(3), pn(3),
		         fn(15), fn(14), fn(13), fn(12),
		         aeqb(3),cn16);

END ADDER;