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Logic Analyzer 的代码
main.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity main is
port (start,choice,clk:in std_logic;
segout:out std_logic_vector(6 downto 0);
cs:out std_l
uart_5kvg_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
uart_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
fifo.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
mul_cpu.vhd
--Copyright (C) 1991-2002 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--
cfg_regs.vhd
--*****************************************************************************
-- FILE : PCI_CFGREG
-- DATE : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr : PCI Configuration Space
pcit_core.vhd
--*****************************************************************************
-- DESIGN : PCI Target Core
-- FILE : PCIT_CORE.vhd
-- DATE : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
--
ddr_command.vhd
--
-- LOGIC CORE: DDR Command module
-- MODULE NAME: ddr_command()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- REVIS
ddr_command.vhd
--
-- LOGIC CORE: DDR Command module
-- MODULE NAME: ddr_command()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- REVIS
ihdlutil.vhd
--
-- interHDL proprietary information
-- Copyright (C) 1990-1998 interHDL inc.
-- All rights reserved.
--
-- ihdlutil package. produced by interVHDL (R)
-- ihdlutil package. Implements utility functi