📄 main.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity main is
port (start,choice,clk:in std_logic;
segout:out std_logic_vector(6 downto 0);
cs:out std_logic_vector(2 downto 0);
alarm:out std_logic;
state:out std_logic_vector(2 downto 0)
);
end;
architecture a of main is
signal startstop,start_fd,choice_fd:std_logic;
signal state1 :std_logic_vector(2 downto 0);
signal state2 :std_logic_vector(2 downto 0);
signal light :std_logic_vector(2 downto 0);
signal count1,count2,count3:std_logic_vector(5 downto 0);
signal num :std_logic_vector(5 downto 0);
signal snum:std_logic_vector(2 downto 0);
signal segout1:std_logic_vector(6 downto 0);
signal cs1:std_logic_vector(2 downto 0);
signal alarm1,clk1,clk2:std_logic;
component fenpin
port (clk:in std_logic;
clk1,clk2:out std_logic);
end component;
component fangdou
port (clk,key:in std_logic;
keyout:out std_logic);
end component;
component display
port(a1:in std_logic_vector(2 downto 0);
a2:in std_logic_vector(5 downto 0);
clk3: in std_logic;
segout:out std_logic_vector(6 downto 0);
cs:out std_logic_vector(2 downto 0));
end component;
begin
g1: fangdou port map (clk2,start,start_fd);
g2: fangdou port map (clk2,choice,choice_fd);
--g3: fangdou port map (clk2,reset,reset_fd);
f1: fenpin port map (clk,clk1,clk2);
d2: process(choice_fd)
begin
if ( choice_fd'event and choice_fd='1' ) then
case state1 is
when "100"=> state2<="010";snum<="010";
when "010"=> state2<="001";snum<="011";
when "001"=> state2<="011";snum<="100";
when "011"=> state2<="111";snum<="101";
when others=> state2<="100";snum<="001";
end case;
end if;
--end if;
end process;
state1<=state2;
d3:process(start_fd)
begin
if (start_fd'event and start_fd='1') then
startstop<=not startstop;
end if;
end process;
d4:process(clk1)
begin
if ( clk1'event and clk1='1') then
if ( startstop='1') then
if (state2(2)='1' and count1(3 downto 0)>"0000") then
count1<=count1-"000001";
num<=count1;
light<="100";
elsif (state2(2)='1' and count1(5 downto 4)>"00") then
count1(5 downto 4)<=count1(5 downto 4)-"01";
count1(3 downto 0)<="1001";
num<=count1;
light<="100";
elsif (state2(1)='1' and count2(3 downto 0)>"0000") then
count2<=count2-"000001";
num<=count2;
light<="010";
elsif (state2(1)='1' and count2(5 downto 4)="01") then
count2(5 downto 4)<="00";
count2(3 downto 0)<="1001";
num<=count2;
light<="010";
elsif (state2(0)='1' and count3(3 downto 0)>"0000") then
count3<=count3-"000001";
num<=count3;
light<="001";
elsif (state2(0)='1' and count3(5 downto 4)="01") then
count3(5 downto 4)<="00";
count3(3 downto 0)<="1001";
num<=count3;
light<="001";
else
light<="000";
num<="000000";
alarm1<='1';
end if;
elsif (startstop='0' and alarm1='1') then
alarm1<='0';
count1<="100000";
count2<="010101";
count3<="010000";
end if;
end if;
end process;
p1: display port map (snum,num(5 downto 0),clk2,segout1,cs1);
segout<=segout1;
cs<=cs1;
alarm<=alarm1;
state<=light;
end;
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