mul_cpu.vhd

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--Copyright (C) 1991-2002 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only to
--program PLD devices (but not masked PLD devices) from Altera.  Any other
--use of such megafunction design, net list, support information, device
--programming or simulation file, or any other related documentation or
--information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner.  Title to
--the intellectual property, including patents, copyrights, trademarks,
--trade secrets, or maskworks, embodied in any such megafunction design,
--net list, support information, device programming or simulation file, or
--any other related documentation or information provided by Altera or a
--megafunction partner, remains with Altera, the megafunction partner, or
--their respective licensors.  No other licenses, including any licenses
--needed under any third party's intellectual property, are provided herein.
--Copying or modifying any file, or portion thereof, to which this notice
--is attached violates this copyright.

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity MUL_cpu is 
        port (
              -- inputs:
                 signal aclr : IN STD_LOGIC;
                 signal clken : IN STD_LOGIC;
                 signal clock : IN STD_LOGIC;
                 signal dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                 signal datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

              -- outputs:
                 signal result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );

end entity MUL_cpu;


architecture europa of MUL_cpu is
component MUL_cpu_black_box_module is 
           port (
                 -- inputs:
                    signal aclr : IN STD_LOGIC;
                    signal clken : IN STD_LOGIC;
                    signal clock : IN STD_LOGIC;
                    signal dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
                    signal datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

                 -- outputs:
                    signal result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
                 );
end component MUL_cpu_black_box_module;

              signal internal_result :  STD_LOGIC_VECTOR (31 DOWNTO 0);

begin

  the_MUL_cpu_black_box_module : MUL_cpu_black_box_module
    port map(
      result => internal_result,
      clken => clken,
      aclr => aclr,
      clock => clock,
      dataa => dataa,
      datab => datab
    );


  --vhdl renameroo for output signals
  result <= internal_result;

end europa;