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找到约 10,000 项符合
Logic Analyzer 的代码
新建 文本文档.txt
程序一：
1． 移位寄存器：
library ieee;
use ieee.std_logic_1164.all;
entity reg is
port(clk,reset:in std_logic;
data:in std_logic_vector(7 downto 0);--输入的数据
outdata:out std_logic_
bel.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bel is
port(ms1,ss1:in std_logic_vector(7 downto 4);
ms2,ss2:in std_logic_
show.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity show is
port(hs1,ms1,ss1:in std_logic_vector(7 downto 4);
hs2,ms2,ss2:in s
display_6_led.vhd
--display_6_led.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display_6_led is
port(din0: in std_logic_vector(3 downto 0);
din1: in std_logic_ve
dff89.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff89 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTO
dff15.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff15 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Dout : OUT STD_LOGIC_VECT
dff8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff8 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_V
mc8051_ramx_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
mc8051_rom_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
weideng.txt
library ieee;
use ieee.std_logic_1164.all;
entity kz is
port(left,right:in std_logic;
lft,rit,lr:out std_logic);
end kz;
architecture kz_arc of kz is
begin
process(left,right)