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Logic Analyzer 的代码
msscomppackage.vhd
-- *****************************************************************************************
-- Components for ARM memory subsystem (simulation)
-- Designed by Ruslan Lepetenok
-- Modified 02.02.20
mulctrlandregs.vhd
--****************************************************************************************************
-- Multiplier control and Partial Sum/Carry registers for ARM core
-- Designed by Ruslan Lepete
multipliertestadder.vhd
--****************************************************************************************************
-- Adder for multiplier tester for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 27.01.
arm7tdmis_top.vhd
--****************************************************************************************************
-- Top entity for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 12.02.2003
multiplier.vhd
--****************************************************************************************************
-- Multiplier for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 12.02.2003
--*********
ctl_1.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Entity ctl_1 is
Port(
wr :in std_logic; -- 作时钟使用
A :in std_logic_vector(15 downto 0); -- 16位地址线
D :in std_logic_vector(7 downto 0); --
ctl_2.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Entity ctl_2 is
Port(
clk :in std_logic; -- 作时钟使用
P1_0 :in std_logic; -- 控制脉冲宽度
T :in std_logic_vector(19 downto 0); -- 20位中间控制信号
Q :
txunit.vhd
-------------------------------------------------------------------------------
-- Title : UART
-- Project : UART
---------------------------------------------------------------------------
top_date_clock.vhd
----------------------------------------------------------------------------------------------------
--This module used as a date-clock counter,it can count second,minute,hour,day,month,year
counter104.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter104 is
Port ( set,rd : in std_logic;
clk : in std_logic;