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找到约 10,000 项符合
Logic Analyzer 的代码
lcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd is
Port ( clk : in std_logic; --4MHZ FROM D12
Reset
operation_unit.vhd
-- ----------------------------------------------------------------------
-----------------------------------------------------------------------------
--Library definitions
----
library ieee;
cufifo.vhd
library IEEE;
use IEEE.Std_logic_1164.all;
entity CuFIFO is
port(
rst, clk : in Std_logic;
wr, rd : in Std_logic; ---写信号，读信号
DataIn : in Std_logic_vector(7
min4_e.vhd
----------------------------------------------------------------------
---- ----
---- min4_e.vhd
trellis1_e.vhd
----------------------------------------------------------------------
---- ----
---- trellis1_e.vhd
divider.vhd
--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
c
dataclk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--****************************
entity dataclk is
port(
clk:in std_logic;
reset:i
ex88.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ex88 IS
PORT
(
in1,in2 : STD_LOGIC_vector;
pout : OUT STD_LOGIC_vector
);
END ex88;
ARCHITECTURE a OF ex88 IS
BEGIN
PR
dataclk.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--****************************
entity dataclk is
port(
clk:in std_logic;
reset:i
division10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division10 is
port(lin:in std_logic_vector(9 downto 0);
clock:in std_logic;