cufifo.vhd

来自「fifo的vhdl代码,比较简单」· VHDL 代码 · 共 37 行

library IEEE;
use IEEE.Std_logic_1164.all;

entity CuFIFO is   
   port(
         rst,	clk : in Std_logic;
         wr,	rd 	: in Std_logic;		---写信号，读信号
         DataIn 	: in Std_logic_vector(7 downto 0);
         DataOut 	: out Std_logic_vector(7 downto 0);  
         EMPTY,FULL : out Std_logic);
end CuFIFO;

architecture V2 of CuFIFO is
   type tmemory is array(0 to 3) of Std_logic_vector(7 downto 0);--定义存储空间
begin

	process(rst,clk)
		variable a,		b :	integer range 0 to 3;  --地址指针
		variable Fifo_mem : tmemory;
		variable x,		y :	std_logic;--存储空间状态控制信号，空、满
	begin
		if rst='1' then DataOut<=(others=>'0');	a:=0;b:=0;x:='0';y:='0';---reset e=1
		elsif clk'EVENT AND clk = '1' then  
				if wr='1' and rd='0' and x='0' then---write
						Fifo_mem(a):=DataIn;	a:=a+1;	y:='1';	EMPTY<='0';
						if a=b then x:='1'; end if;
				elsif wr='0' and rd='1' and y='1' then---read
						DataOut<=Fifo_mem(b);	b:=b+1;	x:='0';	FULL<='0';
						if a=b then y:='0'; end if;
				end if;
				
				if x='0' and y='0' then EMPTY<='1'; DataOut<=(others=>'0');--空
				elsif x='1' and y='1' then FULL<='1';--满
				end if;
		end if;
	end process;
end V2;