operation_unit.vhd

本程序为加密芯片内部加密运算单元部分

-- ----------------------------------------------------------------------

-----------------------------------------------------------------------------
--Library definitions
----
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------
--Entity myand
--

entity myand is                                  -- 与门定义
  port(m,n:in std_logic;
       p:out std_logic);
end entity myand;
--------------------------------------------------------------------------
--Architectures
--
architecture ful of myand is
  begin
    p<=m and n;
end architecture ful;
--------------------------------------------------------------------------
-- Library definitions
----

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
---------------------------------------------------------------------------
-- Entity jianfaqi 
--

entity jianfaqi is                               -- 减法器定义
generic(w:integer:=32);
  port(a,b: in std_logic_vector(0 to 31);
        c0: in std_logic;
        c1: out std_logic;
         z: out std_logic_vector(0 to 31));      -- result of jianfaqi
end entity jianfaqi;

---------------------------------------------------------------------------
--Architectures
--
architecture myact1 of jianfaqi is
  begin 
    P0:process 
         begin
           if a>=b+c0 then
             z<=a-(b+c0);
             c1<='0';
           else
             c1<='1';
             z<=("16#1_0000_0000#")-(b+c0-a);
           end if;
    end process;
end architecture myact1;


----------------------------------------------------------------------------
-- Library definitions
----

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
----------------------------------------------------------------------------
--Entity jia_jianfaqi
--

entity jia_jianfaqi is                           -- 加/减法器定义
generic(w:integer:=32);
port(a1,b1: in std_logic_vector(0 to 31);
        c2: in std_logic;
        sel: in std_logic;
        c11: out std_logic;
        d1: out std_logic_vector(0 to 31));      -- result of jia_jianfaqi
end entity jia_jianfaqi;
----------------------------------------------------------------------------
--Architectures
--
architecture myact2 of jia_jianfaqi is
  begin
    P1:process
         begin
           if sel<= '1' then
             if a1>=b1+c2 then                    
                d1<=a1-(b1+c2);                    
                c11<='0';                        
             else                               
                c11<='1';                        
                d1<=("16#1_0000_0000#")-(b1+c2-a1);
             end if;
           elsif sel<='0' then
             d1<=a1+b1+c2;
               if d1<="16#ffff_ffff#" then
                  c11<='0';
               else
                  c11<='1';
               end if;
           end if;
    end process;
 end architecture myact2;
 
 ----------------------------------------------------------------------------- 
 -- Library definitions                              
 ----                          
                               
 library ieee;                 
 use ieee.std_logic_1164.all;  
 use ieee.std_logic_signed.all;
 -----------------------------------------------------------------------------
 -- Entity declaration                                                        
 --                                                                           
                                                                             
 entity comparator is                          -- 比较器定义
 generic(w:integer:=32);                                                      
 port(x:in std_logic_vector(k-1 downto 0);                                    
      y:in std_logic_vector(k-1 downto 0);                                    
      eout:out std_logic);                     -- result of compare          
 end comparator;                                                              
                                                                             
 -----------------------------------------------------------------------------
 -- Architectures                                                             
 --                                                                           
                                                                             
 architecture arch of comparator is                                           
 begin                                                                        
     P2:process(x,y)                                                             
         variable tmp:std_logic;                                                  
           begin                                                                      
            if tmp='1' then                                                             
             for i in 0 to k-1 loop                                                
                 tmp:=tmp and (x(i) XNOR y(i));                                      
             end loop;
            end if;                                                             
           eout <= tmp;                                                           
     end process;                                                                
 end architecture arch; 
 
 -----------------------------------------------------------------------------
 --Library definitions
 ----
 
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 -----------------------------------------------------------------------------
 --Entity D_trigger          
 --
 
 entity D_trigger is                         -- D触发器定义
   port( D: in std_logic;
         clk1: in std_logic;
         clr: in std_logic;
         Q: out std_logic);                  -- result of D_trigger
 end entity D_trigger;
 -----------------------------------------------------------------------------
 --Architectures
 --
 
 architecture myact3 of D_trigger is
 signal q_temp: std_logic;
   begin
     P3:process(clk1,clr)
        begin  
        if (clr='1') then
            D<='0';
          elsif (clk1'event and clk1='1') then            
            q_temp<=D;
            Q<=q_temp;
         end if;
        end process;
 end architecture myact3;
 ------------------------------------------------------------------------------                
 --Library definitions
 ----
 
 library ieee;
 use ieee.std_logic_1164.all;
 ------------------------------------------------------------------------------
 --Entity mymux
 --
 
 entity mymux is                               --多路选择器定义
   port(e1:in std_logic;
        fi:in std_logic;
        g1:in std_logic;
        h1:out std_logic); 
 end entity mymux;
 -----------------------------------------------------------------------------
 --architectures
 --
 
 architecture a of mymux is
   begin
     process
       begin
       if g1='0' then
         h1<=e1;
       else h1<=f1;
       end if;
     end process;
 end architecture a;
 
 ------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_signed.all;
 
 entity operation_unit is                                           --实体说明，总模块
 generic(w:integer:=32);
 port (---------------------------------------------------------------以下为输入端口说明（共16个）
       clk,reset:in std_logic;
       start_add_subtract:in std_logic;
       add_sub_sel:in std_logic;
       subtractor1_in1,subtractor1_in2:in std_logic_vector(0 to 31);
       subtractor2_in1,subtractor2_in2:in std_logic_vector(0 to 31);
       adder_subtractor3_in1,adder_subtractor3_in2:in std_logic_vector(0 to 31);
       xor1_in1,xor1_in2:in std_logic_vector(0 to 31);
       xor2_in1,xor2_in2:in std_logic_vector(0 to 31);
       xor3_in1,xor3_in2:in std_logic_vector(0 to 31);
       ---------------------------------------------------------------三态端口说明（共3个）
       subtractor1_borrow:buffer std_logic;
       subtractor2_borrow:buffer std_logic;
       adder_subtractor3_borrow:buffer std_logic;
       step8_flag:buffer std_logic;
       ---------------------------------------------------------------以下为输出端口说明（共7个）
       subtractor1_output:out std_logic_vector(0 to 31);
       subtractor2_output:out std_logic_vector(0 to 31);
       adder_subtractor3_output:out std_logic_vector(0 to 31);
       xor1_out:out std_logic_vector(0 to 31);
       xor2_out:out std_logic_vector(0 to 31);
       xor3_out:out std_logic_vector(0 to 31));
 end entity operation_unit;
 architecture ben of operation_unit is
       ---------------------------------------------------------------以下为例化元件声明
   component myand
     port(m,n:in std_logic;
          p:out std_logic);
   end component;
   component jianfaqi
     port(a,b: in std_logic_vector(0 to 31);
        c0: in std_logic;
        c1: out std_logic;
         z: out std_logic_vector(0 to 31));
   end component;
   component jia_jianfaqi
     port(a1,b1: in std_logic_vector(0 to 31);
        c2: in std_logic;
        sel: in std_logic;
        c11: out std_logic;
        d1: out std_logic_vector(0 to 31));
   end component;
   component comparator
     port(x:in std_logic_vector(k-1 downto 0);                                    
          y:in std_logic_vector(k-1 downto 0);                                    
          eout:out std_logic);
   end component;
   component D_trigger
     port( D: in std_logic;
           clk1: in std_logic;
           clr: in std_logic;
           Q: out std_logic);
   end component;
   component mymux
     port(e1:in std_logic;
          fi:in std_logic;
          g1:in std_logic;
          h1:out std_logic);
   end component;
   signal i1,ji,i2,j2,i3,j3,i4,j4,k4 : std_logic;     
        -------------------------------------------------------------------------以下为进程
     
   begin
     P1:process(start_add_subtract)
          begin
          if (start_add_subtract='1') then
            xor1_out<=xor1_in1 xor xor1_in2;
            xor2_out<=xor2_in1 xor xor2_in2;
            xor3_out<=xor3_in1 xor xor3_in2;
          end if;
        end process;
     
     P2:process
            begin
              u1 : D_trigger port map(clk1=>clk,clr=>reset,D=>subtractor2_borrow,Q=>i1);
              u2 : myand port map(m=>i1,n=>start_add_subtract,p=>j1);
              u3 : jianfaqi port map(c0=>j1,a=>subtractor2_in1,b=>subtractor2_in2,c1=>subtractor2_borrow,
                   z=>subtractor2_output);
              u4 : D_trigger port map(clk1=>clk,clr=>reset,D=>subtractor1_borrow,Q=>i2);
              u5 : myand port map(m=>i2,n=>start_add_subtract,p=>j2);
              u6 : jianfaqi port map(c0=>j2,a=>subtractor1_in1,b=>subtractor1_in2,c1=>subtractor1_borrow,
                   z=>subtractor1_output);
              u7 : D_trigger port map(clk1=>clk,clr=>reset,D=>adder_subtractor3_borrow,Q=>i3);
              u8 : myand port map(m=>i3,n=>start_add_subtract,p=>j3);
              u9 : jia_jianfaqi port map(c2=>j3,a1=>adder_subtractor3_in1,b1=>adder_subtractor3_in2,sel=>add_sub_sel,
                   c11=>adder_subtractor3_borrow,d1=>adder_subtractor3_output);
              u10 : comparator port map(x=>subtractor1_in1,y=>subtractor1_in2,eout=>i4);
              u11 : myand port map(m=>i4,n=>step8_flag,p=>j4);
              u12 : mymux port map(g1=>start_add_subtract,e1=>i4,f1=>j4,h1=>k4);
              u13 : D_trigger port map(D=>k4,clk1=>clk,Q=>step8_flag);
        end process;
 end architecture ben;