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jt.vhf
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
-----------------------------------------------------
mux6.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux6 is
port(
s :in std_logic_vector(2 downto 0);
muxin1,muxin2,muxin3,muxin4 : in std_logic_vector(6 d
pcu.vhd
-- ************************************************************************
-- * NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE *
-- *
system.vhd
-- ************************************************************************
-- * NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE *
-- *
pcu.vhd
-- ************************************************************************
-- * NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE *
-- *
system.vhd
-- ************************************************************************
-- * NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE *
-- *
testbench_ac97_package.vhd
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_package.vhd,v 1.1 2005/02/18 15:30:21 wirthlin Exp $
------------------------------------------
ram2rw256xm.vhd
--************************************************************
--************************************************************
--*----------------------------------------------------------*
--*|Vers
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s9 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :=