jt.vhf

交通灯控制,在A和B方向各用数码管显示剩余的时间.

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-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1i
--  \   \         Application : sch2vhdl
--  /   /         Filename : JT.vhf
-- /___/   /\     Timestamp : 04/11/2007 18:27:26
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: C:/Xilinx7.1/bin/nt/sch2vhdl.exe -intstyle ise -family spartan2 -flat -suppress -w JT.sch JT.vhf
--Design Name: JT
--Device: spartan2
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity JT is
   port ( CLK : in    std_logic; 
          RST : in    std_logic; 
          AG  : out   std_logic; 
          AL  : out   std_logic; 
          AR  : out   std_logic; 
          AY  : out   std_logic; 
          BG  : out   std_logic; 
          BL  : out   std_logic; 
          BR  : out   std_logic; 
          BY  : out   std_logic; 
          SEG : out   std_logic_vector (6 downto 0); 
          sel : out   std_logic_vector (3 downto 0));
end JT;

architecture BEHAVIORAL of JT is
   signal XLXN_2  : std_logic_vector (2 downto 0);
   signal XLXN_3  : std_logic_vector (5 downto 0);
   signal XLXN_4  : std_logic_vector (5 downto 0);
   signal XLXN_9  : std_logic_vector (3 downto 0);
   signal XLXN_10 : std_logic_vector (3 downto 0);
   signal XLXN_11 : std_logic_vector (3 downto 0);
   signal XLXN_12 : std_logic_vector (3 downto 0);
   signal XLXN_24 : std_logic;
   signal XLXN_25 : std_logic_vector (1 downto 0);
   signal XLXN_32 : std_logic;
   signal XLXN_90 : std_logic_vector (3 downto 0);
   component djs
      port ( CNT1 : out   std_logic_vector (5 downto 0); 
             CNT2 : out   std_logic_vector (5 downto 0); 
             clk  : in    std_logic; 
             AXS  : in    std_logic_vector (2 downto 0));
   end component;
   
   component jtd
      port ( clk : in    std_logic; 
             rst : in    std_logic; 
             A_R : out   std_logic; 
             A_Y : out   std_logic; 
             A_G : out   std_logic; 
             A_L : out   std_logic; 
             B_R : out   std_logic; 
             B_Y : out   std_logic; 
             B_G : out   std_logic; 
             B_L : out   std_logic; 
             AXS : out   std_logic_vector (2 downto 0));
   end component;
   
   component se
      port ( clk  : in    std_logic; 
             sell : out   std_logic_vector (1 downto 0));
   end component;
   
   component fengliwei
      port ( age  : out   std_logic_vector (3 downto 0); 
             ashi : out   std_logic_vector (3 downto 0); 
             bge  : out   std_logic_vector (3 downto 0); 
             bshi : out   std_logic_vector (3 downto 0); 
             clk  : in    std_logic; 
             cnt1 : in    std_logic_vector (5 downto 0); 
             cnt2 : in    std_logic_vector (5 downto 0));
   end component;
   
   component f1s
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
   component ymq1
      port ( A : in    std_logic_vector (3 downto 0); 
             Q : out   std_logic_vector (6 downto 0));
   end component;
   
   component fpq10ms
      port ( CLK : in    std_logic; 
             CP  : out   std_logic);
   end component;
   
   component xzq5
      port ( Q1  : in    std_logic_vector (3 downto 0); 
             Q2  : in    std_logic_vector (3 downto 0); 
             Q3  : in    std_logic_vector (3 downto 0); 
             Q4  : in    std_logic_vector (3 downto 0); 
             S   : in    std_logic_vector (1 downto 0); 
             sel : out   std_logic_vector (3 downto 0); 
             Q   : out   std_logic_vector (3 downto 0));
   end component;
   
begin
   XLXI_1 : djs
      port map (AXS(2 downto 0)=>XLXN_2(2 downto 0),
                clk=>XLXN_32,
                CNT1(5 downto 0)=>XLXN_3(5 downto 0),
                CNT2(5 downto 0)=>XLXN_4(5 downto 0));
   
   XLXI_4 : jtd
      port map (clk=>XLXN_32,
                rst=>RST,
                AXS(2 downto 0)=>XLXN_2(2 downto 0),
                A_G=>AG,
                A_L=>AL,
                A_R=>AR,
                A_Y=>AY,
                B_G=>BG,
                B_L=>BL,
                B_R=>BR,
                B_Y=>BY);
   
   XLXI_5 : se
      port map (clk=>XLXN_24,
                sell(1 downto 0)=>XLXN_25(1 downto 0));
   
   XLXI_9 : fengliwei
      port map (clk=>XLXN_24,
                cnt1(5 downto 0)=>XLXN_3(5 downto 0),
                cnt2(5 downto 0)=>XLXN_4(5 downto 0),
                age(3 downto 0)=>XLXN_9(3 downto 0),
                ashi(3 downto 0)=>XLXN_10(3 downto 0),
                bge(3 downto 0)=>XLXN_11(3 downto 0),
                bshi(3 downto 0)=>XLXN_12(3 downto 0));
   
   XLXI_36 : f1s
      port map (CLK=>CLK,
                CP=>XLXN_32);
   
   XLXI_38 : ymq1
      port map (A(3 downto 0)=>XLXN_90(3 downto 0),
                Q(6 downto 0)=>SEG(6 downto 0));
   
   XLXI_51 : fpq10ms
      port map (CLK=>CLK,
                CP=>XLXN_24);
   
   XLXI_52 : xzq5
      port map (Q1(3 downto 0)=>XLXN_9(3 downto 0),
                Q2(3 downto 0)=>XLXN_10(3 downto 0),
                Q3(3 downto 0)=>XLXN_11(3 downto 0),
                Q4(3 downto 0)=>XLXN_12(3 downto 0),
                S(1 downto 0)=>XLXN_25(1 downto 0),
                Q(3 downto 0)=>XLXN_90(3 downto 0),
                sel(3 downto 0)=>sel(3 downto 0));
   
end BEHAVIORAL;