pcu.vhd

debussy中文使用手册

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--   Debussy tutorial case: A simplified microprogramming-based CPU
--   file name: ALUB.v
--   description: this part performs the arithmetic and login funtion
--                on the operands of internal data bus(IDB)
--                IR: instruction register (from CCU)
--                IDB: internal data bus (from PCU)
--                PC: program counter (from PCU)
--                C: timing control (from CCU,12-bits)
--                clock: system clock
--                reset: system reset
--                S1: program counter control (to PCU)
--                ALU: ALU output data (to PCU)
--                IXR: index register (to PCU)


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity PCU is
  port (
    ALU : in std_logic_vector(7 downto 0);
    IXR : in std_logic_vector(7 downto 0);
    PC : buffer std_logic_vector(7 downto 0);
    IDB : buffer std_logic_vector(7 downto 0);
    data : inout std_logic_vector(7 downto 0);
    TDB : buffer std_logic_vector(7 downto 0);
    S1 : in std_logic;
    error_in : in std_logic;
    C6 : in std_logic;
    C5 : in std_logic;
    C1 : in std_logic;
    mux_sel : in std_logic_vector(2 downto 0);
    reset : in std_logic
  );
end PCU;

architecture RTL of PCU is
signal IDR     : std_logic_vector(7 downto 0);
signal TR     : std_logic_vector(7 downto 0);
signal n_clk1   : std_logic;
signal TDB0     : std_logic_vector(7 downto 0);


begin

--Tri-state buffer
process (C1)
begin
        if (C1 = '1') then
                data <= (others => 'Z');
        else
                data <= IDR;
        end if;
 end process;


 process (IDR, PC, TR, ALU, IXR, mux_sel)
 begin
        case mux_sel is
        when "000" => IDB <= IDR;
        when "001" => IDB <= PC;
        when "010" => IDB <= TR;
        when "011" => IDB <= ALU;
        when "100" => IDB <= IXR;
        when "101" => IDB <= (others => '0');
        when "110" => IDB <= (others => '0');
        when "111" => IDB <= (others => '0');
        when others => IDB <= (others => 'X');
        end case;
 end process;

 process (IDB, TDB, C1)
 begin
        case C1 is
        when '0' => TDB0 <= IDB after 1 ns;
        when '1' => TDB0 <= TDB after 1 ns;
        when others => TDB0 <= (others => 'X') after 1 ns;
        end case;
 end process;


 process (C5, reset)
 begin
 if (reset ='0') then
        IDR <= "00000000";
-- elsif (falling_edge(C5)) then
  elsif (C5'event and C5 = '0') then
        IDR <= TDB0;
 end if;
 end process;

 process (S1, reset)
 begin
 if (reset ='0') then
        PC <= "00000000";
-- elsif (falling_edge(S1)) then
 elsif (S1'event and S1 = '0') then
        PC <= ALU;
 end if;
 end process;

 process (n_clk1, reset)
 begin
 if (reset ='0') then
        TR <= "00000000";
-- elsif (rising_edge(n_clk1)) then
  elsif (n_clk1'event and n_clk1 = '1') then
        TR <= ALU;
 end if;
 end process;

 n_clk1 <= not(C6);

 process (C1, error_in, data)
 begin
        if (error_in = '1') then
                TDB <= "00000000";
        elsif (C1 = '1') then
                TDB <= data;
        end if;
 end process;
end RTL;