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找到约 10,000 项符合
Logic Analyzer 的代码
alu.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY ALU IS
PORT(
s1,s0: in std_logic;
a: in std_logic_vector(7 downto 0);
b
alu.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY ALU IS
PORT(
s1,s0: in std_logic;
a: in std_logic_vector(7 downto 0);
b
six choose one.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity m6_1scan is
port(
reset : in std_logic;
clkscan : in st
common.vhd
--------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 05/17/2005
-- Copyright : 2005, XESS C
vga.vhd
--------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 05/17/2005
-- Copyright : 2005, XESS C
sdramcntl.vhd
library IEEE, UNISIM;
use IEEE.std_logic_1164.all;
package sdram is
-- SDRAM controller
component sdramCntl
generic(
FREQ : natural := 50_000; -- operating
video.vhd
------------------------------------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 2/9/2006
-- Co
newcoder.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY newCODER IS
PORT(EN: IN STD_LOGIC;
A:IN STD_LOGIC_VECTOR(6 DOWNTO 0);
B:OUT STD_LOGIC_VECTOR(
show.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHOW IS
PORT(CLK_IN:IN STD_LOGIC;
S_IN:IN STD_LOGIC;
LOAD_IN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
c_fenpin.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity c_fenpin is
port(clk:in std_logic;
y:out std_logic);
end;
architecture behav of c