show.vhd

我们学校做VHDL实验的源码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHOW IS
  PORT(CLK_IN:IN STD_LOGIC;
         S_IN:IN STD_LOGIC;
       LOAD_IN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
         EN_IN:IN STD_LOGIC;
         MID :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
          C_OUT:OUT  STD_LOGIC;
             L: OUT STD_LOGIC
       );
END ENTITY;
ARCHITECTURE BHV OF SHOW IS
   COMPONENT SHUMA
     PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       B:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
       W:OUT STD_LOGIC
      );
    END COMPONENT;
   COMPONENT COUNTER
     PORT( CLK:IN STD_LOGIC;
       EN: IN STD_LOGIC;
        S: IN STD_LOGIC;
       LOAD: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          C: OUT STD_LOGIC;
       JISHU: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
     );
  END  COMPONENT;
    SIGNAL D:STD_LOGIC_VECTOR(3 DOWNTO 0);
       BEGIN
         U1:COUNTER PORT MAP( CLK=>CLK_IN,EN=>EN_IN,S=>S_IN,LOAD=>LOAD_IN,JISHU=>D,C=>C_OUT);
         U2:SHUMA PORT MAP(A=>D,B=>MID,W=>L);
       END BHV;