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Logic Analyzer 的代码
interfazv1.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity interfaz is
port (
clk: in STD_LOGIC;
resetz: in STD_LOGIC;
data: in STD_LOGIC_VECTOR(5 downto 0);
habili
fifobuffer.vhd.bak
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY FIFOBuffer IS
PORT(
wclk : IN std_logic;
rstb : IN std_logic;
ISOP : IN std_logic;
IE
fifobuffer.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY FIFOBuffer IS
PORT(
wclk : IN std_logic;
rstb : IN std_logic;
ISOP : IN std_logic;
IE
ddr_command.vhd
--
-- LOGIC CORE: DDR Command module
-- MODULE NAME: ddr_command()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- REVIS
ddr_command.vhd
--
-- LOGIC CORE: DDR Command module
-- MODULE NAME: ddr_command()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- REVIS
ctrl.vhd
--*********************************************
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
LIBRARY altera;
USE altera.maxpl
elec_lock.vhd
--*********************************************
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
LIBRARY altera;
USE altera.maxpl
counter60.vhd
--******************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--****************************
counter24.vhd
--******************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--****************************
rom16_8.vhd
-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*************************************