interfazv1.vhd

用VHDL实现视频控制程序,实现对图像的采集和压缩,

library IEEE;
use IEEE.std_logic_1164.all;

entity interfaz is
    port (
        clk: in STD_LOGIC;
        resetz: in STD_LOGIC;
        data: in STD_LOGIC_VECTOR(5 downto 0);
        habilitador: in STD_LOGIC;
	clear_h: in STD_LOGIC;
	clear_v: in STD_LOGIC;
        href:in STD_LOGIC;
        selecc: in STD_LOGIC;
        hsync: out STD_LOGIC;
        r: out STD_LOGIC_VECTOR (1 downto 0);
        g: out STD_LOGIC_VECTOR (1 downto 0);
        b: out STD_LOGIC_VECTOR (1 downto 0);
        vsync: out STD_LOGIC
        
    );
end interfaz;

architecture ertop_arch of interfaz is

signal Q1:std_logic_vector(9 DOWNTO 0);
signal Q2:std_logic_vector(9 DOWNTO 0);
signal O11,O21,O31,O12,O22,O32: std_logic;
signal clear8,clear9: std_logic;
signal pixel: std_logic_vector(5 downto 0);

component contador_vga is
    generic(N: integer:= 8;satur:integer:=511);
    port (
        clk: in STD_LOGIC;
        enable: in STD_LOGIC;
        resetz: in STD_LOGIC;
        clear: in STD_LOGIC;
        Q: out STD_LOGIC_VECTOR (N DOWNTO 0)
        );
end component;

component COMPARADOR is
     generic (ANCHO: integer := 8;
              EOS : integer := 200;
              SOB : integer := 210;
              EOB : integer := 220;
              EOL : integer := 230 
     );
     port ( data : in std_logic_vector (ANCHO-1 downto 0);
            clk, resetz,href : in std_logic;
            O1, O2, O3 : out std_logic
          );
end component;


component Gencolor is
    port (
	habilitador: in STD_LOGIC;
        blank_h: in STD_LOGIC;
        blank_v: in STD_LOGIC;
        Data: in STD_LOGIC_VECTOR (5 downto 0);
        R: out STD_LOGIC_VECTOR (1 downto 0);
        G: out STD_LOGIC_VECTOR (1 downto 0);
        B: out STD_LOGIC_VECTOR (1 downto 0)
    );
end component;

begin

clear8<=O31 or clear_h;   --Clear horizontal or clear original
clear9<=O32 or clear_v;   --Clear vertical or clear original

cont8: contador_vga

	generic map(N=>9, satur=>(2**10)-1)
	port map(clk=>clk,enable=>habilitador,resetz=>resetz,clear=>clear8,Q=>Q1);

cont9: contador_vga

        generic map(N=>9, satur=>(2**10)-1)
	port map(clk=>clk,resetz=>resetz,enable=>O31,clear=>clear9,Q=>Q2);

comp8: comparador

        generic map(ANCHO=>10,EOS=>640,SOB=>656,EOB=>760,EOL=>832)
	port map(clk=>clk,resetz=>resetz,data=>Q1,O1=>O11,O2=>hsync,O3=>O31,href=>href);

comp9: comparador

        generic map(ANCHO=>10,EOS=>479,SOB=>489,EOB=>491,EOL=>523)
	port map(clk=>clk,resetz=>resetz,data=>Q2,O1=>O12,O2=>vsync,O3=>O32,href=>href);

pixel<= data when selecc='0' else "001100";  --Permite depurar la interfaz

gen:   gencolor

	port map(blank_h=>O11,blank_v=>O12,Data=>pixel,R=>R,G=>G,B=>B, habilitador=>habilitador);
	
end ertop_arch;