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Logic Analyzer 的代码
cnt24.vhd
LIBRARY IEEE; -- 24进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT24 IS
PORT ( CLK,EN, U_D : IN STD_LOGIC;
dds_vhdl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC;
CLK_DA
dds.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC;
DA_CLK : OUT
etester.vhd
LIBRARY IEEE; -- 2004；GWDVPB 选择模式5
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY etester IS
PORT (BCLK : IN STD_LOGIC; --标准频率时钟信号CLOCK2：P124
TCLK : IN STD_L
test.vhd
LIBRARY IEEE; -- 2002/2/1 GWDVPB
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY etester IS
PORT (BCLK : IN STD_LOGIC; --标准频率时钟信号
TCLK : IN STD_LOGIC; --PI
ball.vhd
--乒乓球灯模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ball is
port(clk:in std_logic;--乒乓球灯前进时钟
clr:in std_logic;--乒乓球灯清零
way:in std_logic;--乒乓球灯前进方向
en
dac2adc.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DAC2ADC IS
PORT ( CLK : IN STD_LOGIC; --计数器时钟
LM311 : IN STD_LOGIC; --LM311输出，由PIO37口进入FPG
pc.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PC IS
PORT(
LOAD,LDPC,CLR:IN STD_LOGIC;
D:IN STD_LOGIC_VECTOR(7 DO
mux5.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX5 IS
PORT(
C,D,E,F,G:IN STD_LOGIC;
X0,X1,X2,X3,IALU:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
OMUX5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
wrground.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins