mux5.vhd

在软件MAX+plus II环境中

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX5 IS
PORT(
    C,D,E,F,G:IN STD_LOGIC;
    X0,X1,X2,X3,IALU:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    OMUX5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
     );
END MUX5;
ARCHITECTURE A OF MUX5 IS
SIGNAL SEL:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
  SEL<=G&F&E&D&C;
  PROCESS(SEL)
  BEGIN
    IF(SEL="11110") THEN --输出R0的内容     
      OMUX5<=X0;
    ELSIF(SEL="11101") THEN--输出R1的内容
      OMUX5<=X1;
    ELSIF(SEL="11011") THEN--输出R2的内容
      OMUX5<=X2;
    ELSIF(SEL="10111") THEN--输出R3的内容   
      OMUX5<=X3;
    ELSIF(SEL="01111") THEN--输出ALU的内容
      OMUX5<=IALU;
    ELSE
      NULL;
    END IF;
  END PROCESS;
END A;