mux2_1.vhd

来自「在软件MAX+plus II环境中」· VHDL 代码 · 共 21 行

--从PC和BUS中选择数据到地址寄存器
LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2_1 IS
PORT(
    PC_B:IN STD_LOGIC;
    IPC,IBUS:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    M2_1OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    );
END MUX2_1;
ARCHITECTURE A OF MUX2_1 IS
BEGIN
  
  
    M2_1OUT<=IPC WHEN PC_B='1' ELSE      
      IBUS;   
  
END A;