wrground.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity wrground is
	port(clk:in std_logic;
		RxAv:in std_logic;
		ramwe:in std_logic;
		din:in std_logic_vector(7 downto 0);
		hloc:in std_logic_vector(9 downto 0);
		vloc:in std_logic_vector(9 downto 0);
		we:out std_logic;
		dout:out std_logic_vector(7 downto 0));
end wrground;

architecture Behavioral of wrground is
--component ground is
--	port (
--	addr: IN std_logic_VECTOR(12 downto 0);
--	clk: IN std_logic;
--	din: IN std_logic_VECTOR(7 downto 0);
--	dout: OUT std_logic_VECTOR(7 downto 0);
--	we: IN std_logic);
--end component;

signal readclk:std_logic;
signal sramclk:std_logic;
signal webuf:std_logic;
signal addrbuf:std_logic_vector(12 downto 0);
signal doutbuf:std_logic_vector(7 downto 0);
begin
we<=webuf;

process(clk)
begin
  if clk'event and clk='1' then
    readclk<=not readclk;
  end if;
end process;

process(webuf)
begin
  if webuf='1' then
    sramclk<=RxAv;
  else
    sramclk<=readclk;
  end if;
end process;

process(sramclk,ramwe)
begin
  if ramwe='1' then
    webuf<='1';
    addrbuf<="0000000000000";
  elsif sramclk'event and sramclk='1' then
    if webuf='1' then
      dout<="00000000";
      if addrbuf="1001010111111" then
	  addrbuf<="0000000000000";
	  webuf<='0';
      else
	  addrbuf<=addrbuf+1;
	  webuf<='1';
      end if;
    elsif hloc<=639 and vloc<=479 then 
      dout<=doutbuf;
      case hloc is
	when "1001111111" =>
	  if vloc=59 or vloc=119 or vloc=179 or vloc=239 or vloc=299 or vloc=359 or vloc=419 or vloc=479 then
	    addrbuf<="0000000000000";
	  else
	    addrbuf<=addrbuf+1;
	  end if;
	when "0001001111" =>	  --79
	  addrbuf<=addrbuf-79;
	when "0010011111" =>	  --159
	  addrbuf<=addrbuf-79;
	when "0011101111" =>	  --239
	  addrbuf<=addrbuf-79; 
	when "0100111111" =>	  --319
	  addrbuf<=addrbuf-79;
	when "0110001111" =>   --399
	  addrbuf<=addrbuf-79;
	when "0111011111" =>	  --479
	  addrbuf<=addrbuf-79;
	when "1000101111" =>   --559
	  addrbuf<=addrbuf-79;
	when others => 
	  addrbuf<=addrbuf+1;
      end case;
    elsif vloc>=480 then
      addrbuf<="0000000000000";
      dout<="00000000";
    else
      dout<="00000000";
    end if;
  end if;
end process;

--u0:ground port map
--	(clk=>sramclk,
--	 we=>webuf,
--	 addr=>addrbuf,
--	 din=>din,
--	 dout=>doutbuf);
  
end Behavioral;