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找到约 10,000 项符合
Logic Analyzer 的代码
cont.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cont is
PORT( clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
cont : OUT STD_LOGIC_VECTOR(3 DOW
cnt24.vhd
LIBRARY IEEE; -- 24进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT24 IS
PORT ( CLK,EN, U_D : IN STD_LOGIC;
qiangdaqi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qiangdaqi is
port(clk : in std_logic;
clk2: in std_logic;
sel : in std_logic;
qiangda.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qiangda is
port(data : in std_logic_vector(7 downto 0);
q: buffer std_logic_vector(3 downto 0);
qiangda.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qiangda is
port(data : in std_logic_vector(7 downto 0);
q: buffer std_logic_vector(3 downto 0);
display.vhd
--Author : 屈峥 2002081212
--File Name : DISPLAY.vhd
--Objective : 动态显示
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DISPLAY IS
PORT (A1 : IN ST
已通过仿真的程序.txt
library IEEE;--与门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and1 is
Port (a,b:in std_logic;
y:out std_logic);
end and1;
dljpym.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dljpym is
port(clk:in std_logic;
key_in:in std_logic_vector(13 downto 0);
d
nco.vhd
-----------------------------------------------------------------------------
-- Project Name : NCO
avr_core.vhd
--************************************************************************************************
-- Top entity for AVR core
-- Version 1.11
-- Designed by Ruslan Lepetenok
-- Modified 03.11.200