已通过仿真的程序.txt

此文件里为我多年收集的子程序模块源代码

library IEEE;--与门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity and1 is
    Port (a,b:in std_logic;
	         y:out std_logic);
end and1;

architecture Behavioral of and1 is

begin
process(a,b)
variable temp:std_logic_vector(1 downto 0);
begin
temp:=a&b;
case temp is
  when "00"=>y<='0';
  when "01"=>y<='0';
  when "10"=>y<='0';
  when "11"=>y<='1';
  when others=>y<='-';
end case;
end process;
end Behavioral;

library IEEE;--上同与门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity and2 is
    Port (a,b:in std_logic;
	         y:out std_logic);
end and2;

architecture Behavioral of and2 is
begin
y<=a and b;
end Behavioral;


library IEEE;--上同与门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity and3 is
    Port (a,b:in std_logic;
	         y:out std_logic);
end and3;

architecture Behavioral of and3 is
begin
process(a,b)
begin
if (a='0' and b='0') then y<='0';
  elsif (a='0' and b='1') then y<='0';
  elsif (a='1' and b='0') then y<='0';
  elsif (a='1' and b='1') then y<='1';
  else y<='-';
end  if;
end process;
end Behavioral;


library IEEE;--四与非门（此程序还可通过IF语句完成）
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity four_nand is
    Port (a,b,c,d:in std_logic;
	             y:out std_logic);
end four_nand;

architecture Behavioral of four_nand is
begin
process(a,b,c,d)
variable temp:std_logic_vector(3 downto 0);
begin
temp:=a&b&c&d;
case temp is
  when "0000"=>y<='1';
  when "0001"=>y<='1';
  when "0010"=>y<='1';
  when "0011"=>y<='1';
  when "0100"=>y<='1';
  when "0101"=>y<='1';
  when "0110"=>y<='1';
  when "0111"=>y<='1';
  when "1000"=>y<='1';
  when "1001"=>y<='1';
  when "1010"=>y<='1';
  when "1011"=>y<='1';
  when "1100"=>y<='1';
  when "1101"=>y<='1';
  when "1110"=>y<='1';
  when "1111"=>y<='0';
  when others=>y<='-';
end case;
end process;
end Behavioral;

library IEEE;--上同四与非门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity a7_22 is
    Port (a:in std_logic;
          b:in std_logic;
		y:out std_logic
		 );
end a7_22;
architecture Behavioral of a7_22 is
begin
y<=not(a and b and c and d);
end Behavioral;



library IEEE;--与非门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity nand1 is
    Port (a,b:in std_logic;
	         y:out std_logic);
end nand1;

architecture Behavioral of nand1 is
begin
process(a,b)
variable temp:std_logic_vector(1 downto 0);
begin
temp:=a&b;
case temp is
  when "00"=>y<='1';
  when "01"=>y<='1';
  when "10"=>y<='1';
  when "11"=>y<='0';
  when others=>y<='-';
end case;
end process;
end Behavioral;

library IEEE;--上同与非门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity a7_7 is
    Port (a:in std_logic;
          b:in std_logic;
		y:out std_logic
		 );
end a7_7;

architecture Behavioral of a7_7 is

begin
y<=a nand b;

end Behavioral;

library IEEE;--上同与非门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity a7_7 is
    Port (a:in std_logic;
          b:in std_logic;
		y:out std_logic
		 );
end a7_7;

architecture Behavioral of a7_7 is
begin
process(a,b)
begin
  if (a='0'and b='0') then y<='1';
    elsif (a='0'and b='1') then y<='1';
    elsif (a='1'and b='0') then y<='1';
    elsif (a='1'and b='1') then y<='0';
    else y<='-';注此处y值只能赋'-',而不能赋'z'或'x'否则综合出错！
  end if;
 end process; 
end Behavioral;



library IEEE;--或非门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity nor1 is
    Port (a,b:in std_logic;
	         y:out std_logic);
end nor1;

architecture Behavioral of nor1 is
begin
process(a,b)
begin
if (a='0' and b='0') then y<='1';
  elsif(a='0' and b='1') then y<='0';
  elsif(a='1' and b='0') then y<='0';
  elsif(a='1' and b='1') then y<='0';
  else y<='-';
end if;
end process;
end Behavioral;

library IEEE;--上同或非门（此程序还可通过case语句描述）
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity a7_13 is
    Port (a:in std_logic;
          b:in std_logic;
		y:out std_logic
		 );
end a7-13;
architecture Behavioral of a7_13 is
begin
y<=a nor b;
end Behavioral;


library IEEE;--非门（反相器）
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity not1 is
    Port (a:in std_logic;
	       y:out std_logic);
end not1;

architecture Behavioral of not1 is
begin
mm:process(a)
begin
case a is
  when '0'=>y<='1';
  when '1'=>y<='0';
  when others=>y<='-';
end case;
end process;
end Behavioral;

library IEEE;--上同非门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity not2 is
    Port (a:in std_logic;
	       y:out std_logic);
end not2;

architecture Behavioral of not2 is
begin
process(a)
begin
  if (a='0') then y<='1';
    elsif (a='1') then y<='0';    
    else y<='-';
  end if;
end process;
end Behavioral;

library IEEE;--上同非门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity not3 is
    Port (a:in std_logic;
	       y:out std_logic);
end not3;

architecture Behavioral of not3 is

begin
y<=not a;

end Behavioral;

library IEEE;--或门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity or1 is
    Port (a,b:in std_logic;
	         y:out std_logic);
end or1;

architecture Behavioral of or1 is
begin
process(a,b)
variable temp:std_logic_vector(1 downto 0);
begin
temp:=a&b;
case temp is
  when "00"=>y<='0';
  when "01"=>y<='1';
  when "10"=>y<='1';
  when "11"=>y<='1';
  when others=>y<='-';
end case;
end process;
end Behavioral;

library IEEE;--上同或门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity a7_10 is
    Port (a: in std_logic;
          b: in std_logic;
		y: out std_logic
		 );
end a7_10;

architecture Behavioral of a7_10 is

begin
  y<=a or b;
end Behavioral;

library IEEE;--上同或门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity a7_10 is
    Port (a: in std_logic;
          b: in std_logic;
		y: out std_logic
		 );
end a7_10;

architecture Behavioral of a7_10 is
begin
process(a,b)
begin
  if (a='0' and b='0') then y<='0';
   elsif (a='0' and b='1') then y<='1';
   elsif (a='1' and b='0') then y<='1';
   elsif (a='1' and b='1') then y<='1';
   else y<='-';
  end if;
end process;
end Behavioral;



library IEEE;--同或门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tor is
    Port (a,b:in std_logic;
	         y:out std_logic);
end tor;

architecture Behavioral of tor is
begin
process(a,b)
begin
if (a='0' and b='0') then y<='1';
  elsif(a='0' and b='1') then y<='0';
  elsif(a='1' and b='0') then y<='0';
  elsif(a='1' and b='1') then y<='1';
  else y<='-';
end if;
end process;
end Behavioral;

library IEEE;--上同同或门（此程序还可通过case语句完成）
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity a7_19 is
    Port (a:in std_logic;
          b:in std_logic;
		y:out std_logic
		 );
end a7_19;
architecture Behavioral of a7_19 is
begin
y<=not(a xor b);
end Behavioral;


library IEEE;--异或门
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity xor1 is
    Port (a,b:in std_logic;
	         y:out std_logic);
end xor1;

architecture Behavioral of xor1 is
begin
process(a,b)
begin
if (a='0' and b='0') then y<='0';
  elsif(a='0' and b='1') then y<='1';
  elsif(a='1' and b='0') then y<='1';
  elsif(a='1' and b='1') then y<='0';
  else y<='-';
end if;
end process;
end Behavioral;

library IEEE;--上同异或门（此程序还可通过case语句实现）
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity a7_16 is
    Port (a:in std_logic;
          b:in std_logic;
		y:out std_logic
		 );
end a7_16;
architecture Behavioral of a7_16 is
begin
y<=a xor b;
end Behavioral;



library IEEE;--四选一选择器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux4 is
    Port (d0,d1,d2,d3,a,b:in std_logic;
	                     y:out std_logic);
end mux4;

architecture Behavioral of mux4 is
begin
process(d0,d1,d2,d3,a,b)
variable temp:std_logic_vector(0 to 1);
begin
temp:=b&a;
case temp is
  when "00"=>y<=d0;
  when "01"=>y<=d1;
  when "10"=>y<=d2;
  when "11"=>y<=d3;
  when others=>y<='-';
end case;
end process;
end Behavioral;

library IEEE;--四选一选择器（注意此程序的写法;此程序波形仿真有毛刺如何消除?）
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity a7_25 is
    Port (d0,d1,d2,d3,a,b:in std_logic;
                    y:out std_logic
		);
end a7_25;

architecture Behavioral of a7_25 is
signal sel:std_logic_vector(1 downto 0);
begin
  sel<=b&a;
  y<=d0 when sel="00" else
     d1 when sel="01" else
	d2 when sel="10" else
	d3 when sel="11" else
	'-';--(注不能用'z',原因?注：在编程时不能将'Z'赋予变量，否则不能进行逻辑综合。)
end Behavioral;

library IEEE;--四选一选择器（注意此程序的写法;此程序波形仿真有毛刺如何消除?）
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity a7_25 is
    Port (d0,d1,d2,d3,a,b:in std_logic;
                    y:out std_logic
		);
end a7_25;

architecture Behavioral of a7_25 is
signal sel:integer;
begin
  with sel select 
    y<=d0 when 0,
       d1 when 1,
	  d2 when 2,
	  d3 when 3,
	  '-' when others;
  sel<=0 when b='0' and a='0' else
       1 when b='0' and a='1' else
	  2 when b='1' and a='0' else
	  3 when b='1' and a='1' else
	  4;
end Behavioral;



library IEEE;--四路选通器（注意此程序的格式）
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux4d is
    Port (d0,d1,d2,d3:in std_logic_vector(3 downto 0);--注意此种写法
	          a,b:in std_logic;
	            y:out std_logic_vector(3 downto 0)
	 );
	       
end mux4d;
architecture Behavioral of mux4d is
signal sel:std_logic_vector(1 downto 0);
begin
  sel<=b&a;
  y<=d0 when sel="00" else
     d1 when sel="01" else
     d2 when sel="10" else
     d3 when sel="11" else
     "----";
end Behavioral;


library IEEE;--74LS348编码器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LS348_1 is
    Port (d:in std_logic_vector(7 downto 0);
	       en1:in std_logic;
			 y:out std_logic_vector(2 downto 0);
			 en0,gs:out std_logic
			 );
end LS348_1;

architecture Behavioral of LS348_1 is

begin
process(d,en1)
begin
if en1='1' then y<="111";gs<='1';en0<='1';
  elsif (en1='0' and d="11111111") then y<="111";gs<='1';en0<='0';
  elsif (en1='0' and d(7)='0') then y<="000";gs<='0';en0<='0';
  elsif (en1='0' and d(6)='0') then y<="001";gs<='0';en0<='0';
  elsif (en1='0' and d(5)='0') then y<="010";gs<='0';en0<='0';
  elsif (en1='0' and d(4)='0') then y<="011";gs<='0';en0<='0';
  elsif (en1='0' and d(3)='0') then y<="100";gs<='0';en0<='0';
  elsif (en1='0' and d(2)='0') then y<="101";gs<='0';en0<='0';
  elsif (en1='0' and d(1)='0') then y<="110";gs<='0';en0<='0';
  elsif (en1='0' and d(0)='0') then y<="111";gs<='0';en0<='0';
  else y<="---";gs<='-';en0<='-';
end if;
end process;
end Behavioral;

library IEEE;--74LS348编码器
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity a7_33 is
    Port (d:in std_logic_vector(7 downto 0);
          en1:in std_logic;
		en0,gs:out std_logic;
		y :out std_logic_vector(2 downto 0)
		 );
end a7_33;

architecture Behavioral of a7_33 is

begin
process(d,en1)
begin
 if (en1='1') then en0<='1';gs<='1';y<="111";
  elsif (en1='0' and d="11111111") then	en0<='0';gs<='1';y<="111";
  elsif (d(7)='0') then en0<='0';gs<='0';y<="000";
  elsif (d(6)='0') then en0<='0';gs<='0';y<="001";
  elsif (d(5)='0') then en0<='0';gs<='0';y<="010"; 
  elsif (d(4)='0') then en0<='0';gs<='0';y<="011";
  elsif (d(3)='0') then en0<='0';gs<='0';y<="100";
  elsif (d(2)='0') then en0<='0';gs<='0';y<="101";
  elsif (d(1)='0') then en0<='0';gs<='0';y<="110";
  elsif (d(0)='0') then en0<='0';gs<='0';y<="111";
 end if;
end process;  
end Behavioral;