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Logic Analyzer 的代码
相应加法器的测试向量（test bench).txt
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
eclock.txt
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div1024
port(clk: in std_logic;
f1hz: out std_logic);
end component;
component count60
port(carry: in std_logic;
avr_core.vhd
--************************************************************************************************
-- Top entity for AVR core
-- Version 1.11
-- Designed by Ruslan Lepetenok
-- Modified 03.11.200
ramdatareg.vhd
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepe
counter10.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter10 is
Port ( clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector
print3.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PRINT3 IS
PORT (RDY: BUFFER STD_LOGIC;
B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
TR, CLK, RESET: IN STD_LOGIC;
print4.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PRINT4 IS
PORT (RDY: BUFFER STD_LOGIC;
B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
TR, CLK, RESET: IN STD_LOGIC;
reg32bit.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg is
generic (n : natural := 32);
port (D : in std_logic_vector(31 downto 0);
Clock, Reset, Enable : in std_logic;
Q : out std_logic_vector(31 downt
reg.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity reg is
port(reset,CS,A0,RD,WR:IN STD_LOGIC;
FE,PE,OVERFLOW,RBF,TBE:in STD_LOGIC;
IRQ:OUT STD_LOGIC;