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Logic Analyzer 的代码
top.vhd
library ieee;
use ieee.std_logic_1164.all;
entity top is
port(
f: out std_logic;
si : in std_logic;
sck, clk : in std_logic;
load : in std_logic;
st :out std_logic_vector(8 dow
main.vhd
--************************************************************
--
-- Project Name: Timer
-- File Name : main.vhd(top level)
-- Function : This is a basic timer,
-- use 2 key to adjust
keydetc.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keydetc is
Port ( clk_5ms :in std_logic;
-- clk_1us :in std_logic;
lock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lock is
port(en,d:in std_logic;
q:out std_logic);
end;
architecture d of lock is
begin
process(en,d)
b
sum32.vhd.bak
--------------------------------------------------------------------------------
-- Project Name： DDS_Project
-- File Name： sum32.vhd
-- Create Date: 19:38:27 2008-05-09
-- Engineer: Kun
dds.vhd.bak
--------------------------------------------------------------------------------
-- Project Name： DDS_Project
-- File Name： dds.vhd
-- Create Date: 20:20:15 2008-05-09
-- Engineer: Kun Y
sum32.vhd
--------------------------------------------------------------------------------
-- Project Name： DDS_Project
-- File Name： sum32.vhd
-- Create Date: 19:38:27 2008-05-09
-- Engineer: Kun
dds.vhd
--------------------------------------------------------------------------------
-- Project Name： DDS_Project
-- File Name： dds.vhd
-- Create Date: 20:20:15 2008-05-09
-- Engineer: Kun Y
altera_mf_components.vhd
--
-- Copyright (C) 1988-2002 Altera Corporation
--
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and an
flex10ke_components.vhd
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any