代码搜索结果
找到约 10,000 项符合
Logic Analyzer 的代码
eda.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY EDA IS
PORT( funset:in std_logic;
fqset,clk:in std_logic;
update:out std_logic_vector(7 downto 0));
END ENTITY EDA;
ARCH
clock.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clock IS
PORT (set,date,clo,clk,rst : IN STD_LOGIC;
co1,co2,co3,co4,co5,co6 : OUT STD_LOGIC_VECTO
finish.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
-----------------------------------------------------
finish.vhf
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
-----------------------------------------------------
chk1101.vhd
library ieee;
use ieee.std_logic_1164.all;
entity chk1101 is
port(din: in std_logic_vector(3 downto 0);
clk: in std_logic;
en: in std_logic;
--clr: in std_logic;
ad.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ad is
port
(clk:in std_logic;
reset:in std_logic;
ad_int:in std_logic;
da
count10.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT10 IS
PORT(CLK:IN STD_LOGIC; ----时钟信号
Y0:OUT STD
testadder.vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
adder.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log