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Logic Analyzer 的代码
4xuan1.vhd
LIBRARY IEEE;
USE IEEE. STD_LOGIC_1164.ALL;
ENTITY sixuanyi IS
PORT(i0:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
i1:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
i2:IN STD_LOGIC_VECTOR (7 DOWNTO
testbenchri.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity instr_reg_test is
end entity;
architecture arch of instr_reg_test is
signal done : boolean := fa
bancregistre.vhdl
LIBRARY ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity reg_file is
port( clk: in std_logic;
testbenchregflag.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity status_reg_test is
end entity;
architecture arch of status_reg_test is
signal done : boolean := false;
signal p
testbenchri.vhdl.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity instr_reg_test is
end entity;
architecture arch of instr_reg_test is
signal done : boolean := false;
signal pass
ncofsymbol.cmp
-- Generated by NCO 7.2 [Altera, IP Toolbench 1.3.0 Build 203]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ********
dsp_port80m.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : dsp_port
-- Design : RC_CKJH
-- Author : 杨云龙
-- Company : 北京百
div5.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
dsp_port.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : dsp_port
-- Design : RC_CKJH
-- Author : 杨云龙
-- Company : 北京百
eda.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY EDA IS
PORT( funset:in std_logic;
fqset,clk:in std_logic;
update:out std_logic_vector(7 downto 0));
END ENTITY EDA;
ARCH