4xuan1.vhd

来自「老师给我们的vhdl源代码」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE. STD_LOGIC_1164.ALL;
ENTITY sixuanyi IS
    PORT(i0:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
           i1:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
           i2:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
           i3:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
           s0:IN STD_LOGIC;
           s1:IN STD_LOGIC;
           y:OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END sixuanyi;

ARCHITECTURE one OF sixuanyi IS
      SIGNAL sel:STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN 
     sel<=s1&s0;
     WITH sel SELECT               
          y<= i0  WHEN "00",
              i1  WHEN "01",
              i2  WHEN "10",
              i3  WHEN OTHERS;
                     
END one;