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Logic Analyzer 的代码
sum32.vhd
--------------------------------------------------------------------------------
-- Project Name： DDS_Project
-- File Name： sum32.vhd
-- Create Date: 19:38:27 2008-05-09
-- Engineer: Kun
dds.vhd
--------------------------------------------------------------------------------
-- Project Name： DDS_Project
-- File Name： dds.vhd
-- Create Date: 20:20:15 2008-05-09
-- Engineer: Kun Y
sum.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
adder_variety_style.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
mc8051_ramx_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXX
mc8051_rom_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXX
cpu_16.vhdl
library IEEE;
library UNISIM;
use ieee.std_logic_1164.all;
use UNISIM.VComponents.all;
entity CPU_16 is
port(
clk: in std_logic;
RST: in std_logic;
Dbus: inout std_logic_vector(15 dow
picoblaze_pwm_control.vhd
--
-- Reference design - Pulse Width Modulation (PWM) using PicoBlaze software and
-- interrupts only on the Spartan-3E Starter Kit.
--
-- Ken Chapman - Xilinx Ltd - 22nd May 2
hdb3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hdb3 is
port(reset,clk,codein: in std_logic;
codeout: out std_logic_vector(1 downto 0));
end hd
加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log