sum.vhdl

这是一个用VHDL写的简易的CPU的程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;

entity sum is
    Port ( adress : out std_logic_vector(15 downto 0);
           sdata : inout std_logic_vector(15 downto 0);
			  sir,spc:out std_logic_vector(15 downto 0);
			  sreg0,sreg7,smdrl:out std_logic_vector(7 downto 0);
			  lig: out std_logic_vector(1 downto 0);
           clkg : in std_logic;
           ncs : out std_logic;
           nwr : out std_logic;
           nrd : out std_logic;
           nbl : out std_logic;
           nbh : out std_logic;
           reset : in std_logic);
end sum;

architecture Behav of sum is
	component bufgp is
		port(I:in std_logic;O:out std_logic);
	end component;
	component clock is
	Port ( clk : in std_logic;
           reset : in std_logic;
           t0 : out std_logic;
           t1 : out std_logic);
	end component;

	component cu is
	Port ( t1 : in  STD_LOGIC;
           databus : in  STD_LOGIC_VECTOR (7 downto 0);
           op : in  STD_LOGIC_VECTOR (4 downto 0);
           reset : in  STD_LOGIC;
           control : out  STD_LOGIC_VECTOR (22 downto 0));
	end component;

	component ieu is
    Port ( cri : in std_logic_vector(2 downto 0);
           crj : in std_logic_vector(2 downto 0);
           istr : in std_logic_vector(4 downto 0);
           ld: out std_logic_vector(7 downto 0);
		 	  resours:out std_logic_vector(3 downto 0));
  	end component;

	component msi is
	Port ( mci : in std_logic_vector(4 downto 0);
           t0 : in std_logic;
           ncs : out std_logic;
           nwr : out std_logic;
           nrd : out std_logic;
           nbl : out std_logic;
           nbh : out std_logic;
			  readm:out std_logic;
			  writem:out std_logic);
	end component;

	signal ld :std_logic_vector(7 downto 0);
	signal readm,writem,t1,t0,clk:std_logic;
	signal ctrlbus:std_logic_vector(3 downto 0);
	signal mir:std_logic_vector(22 downto 0);

	signal reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7,f1,f2,acc,databus:std_logic_vector(7 downto 0):="00000000";
	signal mdr,mar,ir,pc:std_logic_vector(15 downto 0):="0000000000000000";


begin
	--adress<=mar;
u1:clock port map(clk=>clk,reset=>reset,t0=>t0,t1=>t1);
u2:cu  port map(t1=>t1,databus=>databus,op(4 downto 0)=>ir(15 downto 11),reset=>reset,control(22 downto 0)=>mir(22 downto 0)); 
u3:ieu port map(	cri(2 downto 0)=>ir(10 downto 8),
						crj(2 downto 0)=>ir(2 downto 0),
						istr(4 downto 0)=>mir(22 downto 18),
						ld(7 downto 0)=>ld(7 downto 0),
						resours(3 downto 0)=>ctrlbus(3 downto 0));
u4:msi port map(mci(4 downto 0)=>mir(6 downto 2),
						t0=>t0,ncs=>ncs,nwr=>nwr,nrd=>nrd,nbl=>nbl,nbh=>nbh,readm=>readm,writem=>writem);
u5:bufgp port map(I=>clkg,O=>clk);
--operation of acc						
		process(mir(1 downto 0),f1,f2)
		begin
			case mir(1 downto 0) is
			when "00"=>acc<=f1+f2;
			when "01"=>acc<=f1-f2;
			when "10"=>acc<=f1 and f2;
			when "11"=>acc<=f1 or f2;
			when others=>null;
			end case; 
		end process;
		
		process(t0,mir(11))
		begin
			if mir(11)='0' then
			null;
			elsif t0='0' and t0'event then
			f1<=databus;
			end if;
		end process;
		process(t0,mir(10))
		begin
			if mir(10)='0' then 
			null;
			elsif t0='0' and t0'event then
			f2<=databus;
			end if;
		end process;
--operation of databus
		process(ctrlbus,t0)
		begin
		if t0='1' and t0'event then
			case ctrlbus is
			when"1000"=>databus<=reg0;
			when"1001"=>databus<=reg1;
			when"1010"=>databus<=reg2;
			when"1011"=>databus<=reg3;
			when"1100"=>databus<=reg4;
			when"1101"=>databus<=reg5;
			when"1110"=>databus<=reg6;
			when"1111"=>databus<=reg7;
			when"0100"=>databus<=ir(7 downto 0);
			when"0111"=>databus<=acc;
			when"0101"=>databus<=mdr(15 downto 8);
			when"0110"=>databus<=mdr(7 downto 0);
			when others=>null;
			end case;
		end if;
		end process;
--operation of reg		
		process(t0,ld(0))
		begin
			if ld(0)='0' then 
			null;
			elsif t0='0' and t0'event then
			reg0<=databus;
			end if;
		end process;
					
		process(t0,ld(1))
		begin
			if ld(1)='0' then 
			null;
			elsif t0='0' and t0'event then
			reg1<=databus;
			end if;
		end process;
	
		process(t0,ld(2))
		begin
			if ld(2)='0' then 
			null;
			elsif t0='0' and t0'event then
			reg2<=databus;
			end if;
		end process;	
	
		process(t0,ld(3))
		begin
			if ld(3)='0' then 
			null;
			elsif t0='0' and t0'event then
			reg3<=databus;
			end if;
		end process;	
	
		process(t0,ld(4))
		begin		
			if ld(4)='0' then 
			null;
			elsif t0='0' and t0'event then
			reg4<=databus;
			end if;
		end process;	
		
		process(t0,ld(5))
		begin
			if ld(5)='0' then 
			null;
			elsif t0='0' and t0'event then
			reg5<=databus;
			end if;
		end process;	
	
		process(t0,ld(6))
		begin
			if ld(6)='0' then 
			null;
			elsif t0='0' and t0'event then
			reg6<=databus;
			end if;
		end process;	
		
		process(t0,ld(7))
		begin
			if ld(7)='0' then 
			null;
			elsif t0='0' and t0'event then
			reg7<=databus;
			end if;
		end process;
--operation	of ir
----mdr->ir
	process(t0,mir(12))
	begin
		if mir(12)='0' then
		null;
		elsif t0='0' and t0'event then
		ir<=mdr;
		end if;
	end process;

--operation of cp

-----pc+1
	process(t0,mir(9),reset)
	begin
		if reset='1' then
		pc<="0000000000000000";
		elsif t0='0' and t0'event then
			case mir(9 downto 7) is
			when"100"=>pc<=pc+1;
			when"010"=>pc(15 downto 8)<=databus;
			when"001"=>pc(7 downto 0)<=databus;
			when others=>null;
			end case;
		end if; 
	end process;

--operation of mar
	process(readm,writem,mar)
	begin
		if readm='1' or writem='1' then
		adress<=mar;
		else
		adress<="ZZZZZZZZZZZZZZZZ";
		end if;
	end process;
----pc->mar
	process(t0,mir)
	begin
		if t0='0' and t0'event then
			if mir(13)='1' then
			mar<=pc;
			elsif mir(17)='1' then
			mar(15 downto 8)<=databus;
			elsif mir(16)='1' then
			mar(7 downto 0)<=databus;
			else
			null;
			end if;
	 	end if;
	end process;
--operation of mdr
	process(t1,readm,writem,t0,mdr)
	begin
		if readm='1' then
			null;
		elsif writem='0' then 
			sdata<="ZZZZZZZZZZZZZZZZ";
		elsif t0='1' then
			sdata<=mdr;
		end if;
		if t1='0' and t1'event then
			if readm='1' then
				mdr<=sdata;
				sdata<="ZZZZZZZZZZZZZZZZ";
			else	
				case mir(15 downto 14) is
				when"10"=>mdr(15 downto 8)<=databus(7 downto 0);
				when"01"=>mdr(7 downto 0)<=databus(7 downto 0);
				when others=>null;
				end case;
			end if;
		end if;
	end process;
	sir<=ir;
	spc<=pc;
	smdrl<=mdr(15 downto 8);
	sreg0<=reg0;
	sreg7<=reg7;
	lig(1)<=t1;
	lig(0)<=t0;

end Behav;