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找到约 10,000 项符合
Logic Analyzer 的代码
elec_lock.vhd
--*********************************************
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
LIBRARY altera;
USE altera.maxpl
mc8051_ramx_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
mc8051_rom_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
driver.vhd
library ieee;
use ieee.std_logic_1164.all; --引用库
USE ieee.std_logic_arith.ALL;
entity Driver is
port(Efficiant: out std_logic; --输出相素有效
Latch:out std_logic; --输出Latch
a8255.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY a8255 IS
PORT(
RESET : IN std_logic;
CLK : IN std_logic;
nCS : IN std_logic;
nRD : IN std_logic;
nWR
division.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity division is
generic(SIZE: INTEGER := 8);
port(reset: in STD_LOGI
example7-6.vhd
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test3 IS
PORT (in1, in2, in3 : IN Std_Logic;
in4 : IN Std_Logic;
out1 : BUFFER Std_Logic);
END test3;
ARCHITECTURE example3 O
example11-26.vhd
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE pak IS
PROCEDURE add (in1, in2 : IN Std_Logic_Vector;
carry_in : IN Std_Logic;
sum : OUT Std_Logic_Vector;
example15-4.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
ENTITY ttest IS
END ttest;
ARCHITECTURE ttest OF ttest IS
COMPONENT detector
PORT(
d21_d:IN std_logic;
d21_c:IN std
example10-4.vhd
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE WORK.pak.ALL;
ENTITY comparator IS
GENERIC (delay : TIME);
PORT (n, m : IN Std_Logic_Vector (1 DOWNTO 0);
ge, le, e, g, l : OUT Std_Log