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Logic Analyzer 的代码
加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
一个简单的uart.txt
----------------------------------------------------------------
--
-- Copyright (c) 1992,1993,1994, Exemplar Logic Inc. All rights reserved.
--
---------------------------------------------------
weideng.txt
library iee;
use iee.std_logic_1164.all;
entity kong is
port(left,right:in std_logic;
lft,rig lr: out std_locic);
end kong
architecture kon_arc of kong is
begin
process(left,right)
va
miniuart.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to th
txunit.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to th
xspcore.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspuc.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspusb.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
muxcmp.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY muxcmp IS
PORT(HH,HL,MH,ML,SH,SL,AHH,AHL,AMH,AML:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s,modes:IN STD_LOGIC_V
muxcmp.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY muxcmp IS
PORT(HH,HL,MH,ML,SH,SL,AHH,AHL,AMH,AML:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s,modes:IN STD_LOGIC_V