📄 muxcmp.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY muxcmp IS
PORT(HH,HL,MH,ML,SH,SL,AHH,AHL,AMH,AML:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s,modes:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
clk:IN STD_LOGIC;
muxout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
alarm:OUT STD_LOGIC);
END muxcmp;
ARCHITECTURE arc OF muxcmp IS
SIGNAL q:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
muxout<=q;
PROCESS(modes)
VARIABLE num:INTEGER range 0 TO 5;
BEGIN
num:=CONV_INTEGER(modes);
CASE num IS
WHEN 0|1|2|3=>
IF(s="010")THEN
q<=HH;
ELSIF(s="011")THEN
q<=HL;
ELSIF(s="100")THEN
q<=MH;
ELSIF(s="101")THEN
q<=ML;
ELSIF(s="110")THEN
q<=SH;
ELSIF(s="111")THEN
q<=SL;
END IF;
WHEN OTHERS=>
IF(s="010")THEN
q<="1010";
ELSIF(s="011")THEN
q<="1100";
ELSIF(s="100")THEN
q<=AHH;
ELSIF(s="101")THEN
q<=AHL;
ELSIF(s="110")THEN
q<=AMH;
ELSIF(s="111")THEN
q<=AML;
END IF;
END CASE;
END PROCESS;
PROCESS(HH,HL,MH,ML,AHH,AHL,AMH,AML)
BEGIN
IF(HH=AHH AND HL=AHL AND MH=AMH AND ML=AML)THEN
alarm<=clk;
ELSE alarm<='0';
END IF;
END PROCESS;
END arc;
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