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Logic Analyzer 的代码
select_32.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
entity select_32 is
port( A:in std_logic_vector(15 downto 0);
B:in std_logic_vector(15 downto 0);
S:in std_logic;
Y:out std_logic_vector(15
timec.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY timec IS
PORT( seca: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
secb: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
mina: IN STD
ddr_sdram.cmp
-- Generated by DDR SDRAM Controller 6.1 [Altera, IP Toolbench v1.3.0 build70]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE
ncoip.cmp
-- Generated by NCO 2.2.1 [Altera, IP Toolbench v1.2.7 build38]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- *******
fff.cmp
-- Generated by FIR Compiler 6.1 [Altera, IP Toolbench v1.3.0 build70]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
kcpsm2.vhd
-- Constant (K) Coded Programmable State Machine for Virtex-II Devices
--
-- Version : 1.0
-- Version Date : 13th December 2001
--
-- Start of design entry : 15th October 2001
--
-- Ken Chapman
pulse.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pulse is
port(
clock: in std_logic;
load: in std_logic;
counter_a
vgadriver.vhd
---------------------------------------------------------------------
-- vga_main.vhd Demo VGA configuration module.
---------------------------------------------------------------------
-- Autho
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity RegFile is
port(
RsData : out vl_logic_vector(31 downto 0);
RtData : out vl_logic_vector(31 downto 0);
uart_5kvg_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE