pulse.vhd

脉冲发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pulse is
port(
   clock:   in std_logic;
   load:    in std_logic;
   counter_able:  in std_logic;
   h_data:    in std_logic_vector(7 downto 0);
   l_data:    in std_logic_vector(7 downto 0);
   channel:  out std_logic
   );
end pulse;
architecture pulse_behave of pulse is
component counter
port(
     clk:     in std_logic;
     enable:        in std_logic;
     load:         in std_logic;
     co:          out std_logic;
     data:      in std_logic_vector(7 downto 0);
     q:      buffer std_logic_vector(7 downto 0)
     );
end component;
signal en_in,pr,c:  std_logic;
signal inter1,inter2: std_logic;
signal q1,q2: std_logic_vector(7 downto 0);
begin
u1:counter port map(clk=>clock,enable=>en_in,load=>pr,
co=>inter1,data=>h_data,q=>q1);
u2:counter port map(clk=>clock,enable=>inter1,load=>pr,
co=>inter2,data=>l_data,q=>q2);
process(clock)
begin
if rising_edge(clock) then
  if q1="00000000" and q2="00000000" then
   c<='1';
  else
   c<='0';
  end if;
end if;
end process;
en_in<=counter_able and (not inter1);
pr<=load or c;
channel<=inter1;
end pulse_behave;