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Logic Analyzer 的代码
vgamem.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity vgamem is
port
(
reset: in std_logic; -- reset
clock: in std_logic; -- VGA dot clock
hsyncb: buffer
test_data_gen.vhd
-- Copyright (C) 2004-2005 Digish Pandya
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License a
jieguo.vhd
--显示输出，包括停车位个数和点阵信息
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jieguo is
port(
clk : in std_logic;
cheweikong: in std_logic;
led
tingche.vhd
--此模块实现车的任意位置停放或离开，并显示剩余车位数量
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity tingche is
port(
clk : in std_logic;
hel
cpu.vhd
library ieee;
use ieee.std_logic_1164.all;
entity cpu is port (
rst : in std_logic;
p12mhz : in std_logic;
--xp12mhz : out std_logic;
rst_cpu : out std_logic;
my_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div1024--1Hz_generator component
Port( clk: in std_logic;--from system clock(1024Hz)
f1hz : out std_logic);-- 1H
shiftrne.vhd
--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port (
r : i
divider.vhd
--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
c
shiftlne.vhd
--shiftlne.vhd n-bitright-to-left shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftlne is
generic ( n : integer := 7 ) ;
port(
r : in s
daima.txt
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
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