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找到约 10,000 项符合 Logic Analyzer 的代码

serparser.vhd

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; -- Uncomment the following lines to use the declarations that are -- provided for instantia

juntos.vhd

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; -- Uncomment the following lines to use the declarations that are -- provided for instantia

加法器源程序.vhd

------------------------------------------------------------------------ -- Single-bit adder ------------------------------------------------------------------------ library IEEE; use IEEE.std_log

加法器描述.txt

-- A Variety of Adder Styles -- download from: www.fpga.com.cn & www.pld.com.cn ------------------------------------------------------------------------ -- Single-bit adder -----------------------

相应加法器的测试向量(test bench).vhd

-- download from: www.pld.com.cn & www.fpga.com.cn entity testbench is end; ------------------------------------------------------------------------ -- testbench for 8-bit adder ------------

counter32b.vhd

LIBRARY IEEE; --32位计数器 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER32B IS PORT (FIN : IN STD_LOGIC; --时钟信号 CLR : IN STD_LOGIC;

mux4_1.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4_1 IS PORT( i0,i1,i2,i3,a,b:IN STD_LOGIC; q:OUT STD_LOGIC); END mux4_1; ARCHITECTURE be OF mux4_1 IS SIGNAL sel:STD_LOG

相应加法器的测试向量(test bench).vhd

-- download from: www.pld.com.cn & www.fpga.com.cn entity testbench is end; ------------------------------------------------------------------------ -- testbench for 8-bit adder ------------

加法器源程序.vhd

------------------------------------------------------------------------ -- Single-bit adder ------------------------------------------------------------------------ library IEEE; use IEEE.std_log

相应加法器的测试向量(test bench).vhd

-- download from: www.pld.com.cn & www.fpga.com.cn entity testbench is end; ------------------------------------------------------------------------ -- testbench for 8-bit adder ------------