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Logic Analyzer 的代码
gh_mult_ip_usus_mg.vhd
-----------------------------------------------------------------------------
-- Filename: gh_mult_ip_usus_mg.vhd
--
-- Description:
-- an inplace multiplier unsigned inputs
-- with modif
usbcomm.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity USBcomm is
port(
--FPGA信号
A: in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
DIN: in STD_LOGIC_VECTOR(7 downto 0); -
led.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LED is
port(
A : in STD_LOGIC_VECTOR(15 downto 0); -- 地址总线
WR : in STD_LOGIC; -- 写使能
DWR : in STD_LOGIC_VECTOR(
txmittest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity txmittest is
port(
tx:out std_logic;
txclkout:out std_logic;--For test send clok;
data:in std_logic_vecto
division10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity division10 is
port(lin:in std_logic_vector(9 downto 0);
clock:in std_logic;
avr_core.vhd
--************************************************************************************************
-- Top entity for AVR core
-- Version 1.11
-- Designed by Ruslan Lepetenok
-- Modified 03.11.200
ramdatareg.vhd
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepe
m_vhdl.txt
伪随机序列发生器的vhdl算法
设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIG
clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clock is
port(
s0,s1:in std_logic;
quickclk:in std_logic;
slowclk:in std
traffic_ctr.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity traffic_ctr is
port(clk:in std_logic;
dalu_dengse,xiaolu_dengse:out std_logic_vector(2 downto 0);