📄 traffic_ctr.txt
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity traffic_ctr is
port(clk:in std_logic;
dalu_dengse,xiaolu_dengse:out std_logic_vector(2 downto 0);
dalu_shijianl,xiaolu_shijianl:out std_logic_vector(3 downto 0);
dalu_shijianh,xiaolu_shijianh:out std_logic_vector(3 downto 0));
end;
architecture a of traffic_ctr is
signal zdd:std_logic_vector(2 downto 0);
signal zxd:std_logic_vector(2 downto 0);
signal zds:std_logic_vector(7 downto 0);
signal zxs:std_logic_vector(7 downto 0);
signal ss:std_logic;
signal m:std_logic;
begin
process(clk)
begin
if clk'event and clk='1' then
if m='0'then
--if zds>"00100111" or zxs>"00110000" then
zds<="00100111";zdd<="001";
zxs<="00110000";zxd<="100";
m<='1';
else
if zds="00000001" and zxs="00000100" then
zds<="00000011";zdd<="010";
zxs<="00000011";zxd<="100";
ss<='0';m<='1';
elsif zds="00000001" and zxs="00000001" and ss='0' then
zds<="00100000";zdd<="100";
zxs<="00010111";zxd<="001";
ss<='0';m<='1';
elsif zds="00000100" and zxs="00000001" then
zds<="00000011";zdd<="100";
zxs<="00000011";zxd<="010";
ss<='1';m<='1';
elsif zds="00000001" and zxs="00000001" and ss='1' then
zds<="00100111";zdd<="001";
zxs<="00110000";zxd<="100";
ss<='0';m<='1';
elsif zds(3 downto 0)=0 then
zds<=zds-7;
zxs<=zxs-1;
elsif zxs(3 downto 0)=0 then
zxs<=zxs-7;
zds<=zds-1;
else zds<=zds-1;
zxs<=zxs-1;
end if;
end if;
end if;
end process;
dalu_dengse<=zdd;
xiaolu_dengse<=zxd;
dalu_shijianl<=zds(3 downto 0);
xiaolu_shijianl<=zxs(3 downto 0);
dalu_shijianh<=zds(7 downto 4);
xiaolu_shijianh<=zxs(7 downto 4);
end;
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