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Logic Analyzer 的代码
ps2.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity PS2 is
port ( KBdata: in STD_LOGIC;
KBCLK: in STD_LOGIC;
DOUT: out STD_LOGIC_VEC
与非门_hct00.vhd
--Quad 2-input Nand
--Simple concurrent model of a TTL quad nand gate.
--uses 1993 std VHDL
library IEEE;
use IEEE.Std_logic_1164.all;
entity HCT00 is
port(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logi
加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
count_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
ledcontrol.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ledcontrol IS
PORT(
reset,clk,urgen : IN STD_LOGIC;
state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
sub,s
ledshow.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ledshow IS
PORT(
clk,urgen : IN STD_LOGIC;
state : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
sub,set1,set2
ledc~578.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ledcontrol IS
PORT(
reset,clk,urgen : IN STD_LOGIC;
state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
sub,s
leddrv.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY leddrv IS
PORT
(
ms10 :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sec :IN STD_LOGIC_VECTOR(7 DOWNTO 0)
cpu.vhd
library ieee;
use ieee.std_logic_1164.all;
entity cpu is port (
rst : in std_logic;
p12mhz : in std_logic;
--xp12mhz : out std_logic;
rst_cpu : out std_logic;