coregen.xml

含有各类寄存器

<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
	<Folder label="VERILOG Component Instantiation" treetype="folder">
		<Template label="fft_2s" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
fft_2s YourInstanceName (
    .clk(clk),
    .ce(ce),
    .reset(reset),
    .start(start),
    .fwd_inv(fwd_inv),
    .mrd(mrd),
    .mwr(mwr),
    .xn_re(xn_re),
    .xn_im(xn_im),
    .ovflo(ovflo),
    .done(done),
    .edone(edone),
    .busy(busy),
    .xk_re(xk_re),
    .xk_im(xk_im));

 
		</Template>
		<Template label="counter" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
counter YourInstanceName (
    .Q(Q),
    .CLK(CLK),
    .UP(UP),
    .LOAD(LOAD),
    .L(L),
    .CE(CE),
    .ACLR(ACLR));

 
		</Template>
	</Folder>
	<Folder label="VHDL Component Instantiation" treetype="folder">
		<Template label="fft_2s" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component fft_2s
    port (
    clk: IN std_logic;
    ce: IN std_logic;
    reset: IN std_logic;
    start: IN std_logic;
    fwd_inv: IN std_logic;
    mrd: IN std_logic;
    mwr: IN std_logic;
    xn_re: IN std_logic_VECTOR(7 downto 0);
    xn_im: IN std_logic_VECTOR(7 downto 0);
    ovflo: OUT std_logic;
    done: OUT std_logic;
    edone: OUT std_logic;
    busy: OUT std_logic;
    xk_re: OUT std_logic_VECTOR(7 downto 0);
    xk_im: OUT std_logic_VECTOR(7 downto 0));
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : fft_2s
        port map (
            clk =&gt; clk,
            ce =&gt; ce,
            reset =&gt; reset,
            start =&gt; start,
            fwd_inv =&gt; fwd_inv,
            mrd =&gt; mrd,
            mwr =&gt; mwr,
            xn_re =&gt; xn_re,
            xn_im =&gt; xn_im,
            ovflo =&gt; ovflo,
            done =&gt; done,
            edone =&gt; edone,
            busy =&gt; busy,
            xk_re =&gt; xk_re,
            xk_im =&gt; xk_im);
 
		</Template>
		<Template label="counter" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component counter
    port (
    Q: OUT std_logic_VECTOR(7 downto 0);
    CLK: IN std_logic;
    UP: IN std_logic;
    LOAD: IN std_logic;
    L: IN std_logic_VECTOR(7 downto 0);
    CE: IN std_logic;
    ACLR: IN std_logic);
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : counter
        port map (
            Q =&gt; Q,
            CLK =&gt; CLK,
            UP =&gt; UP,
            LOAD =&gt; LOAD,
            L =&gt; L,
            CE =&gt; CE,
            ACLR =&gt; ACLR);
 
		</Template>
	</Folder>
</RootFolder>