代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/235210/14081732
vhd onewire2.vhd
---------------------------------------------------------------------------
-- Copyright (c) 2001,2002 White Bream
---------------------------------------------------------------------------
-- DO
www.eeworm.com/read/235210/14081735
vhd onewire1.vhd
---------------------------------------------------------------------------
-- Copyright (c) 2001,2002 White Bream
---------------------------------------------------------------------------
-- DO
www.eeworm.com/read/202599/15377928
vhd ascenseur.vhd
library ieee;
use ieee.std_logic_1164.all;
package ascenseur is
component cabine
port
(AP1,AP2,AP3,AP4 :in std_logic;
ET1,ET2,ET3,ET4,p :in std_logic;
M,D
www.eeworm.com/read/201013/15418348
vhd poc.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity poc is
port(
clk,rdy:in std_logic;
d:in std_logic_vector(7 downto 0);
tr:out std_logic;
pd:out std_logic_ve
www.eeworm.com/read/112807/15476245
vhd pci_cmdadr.vhd
--*****************************************************************************
-- FILE : PCI_CMDADR.vhd
-- DATE : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr : PCI Command Decoder
www.eeworm.com/read/109665/15552507
cmp ethernet_mac.cmp
--Copyright (C) 1991-2002 Altera Corporation
--Any megafunction design, and related netlist (encrypted or decrypted),
--support information, device programming or simulation file, and any oth
www.eeworm.com/read/103567/15728927
vhd ddr_data_path.vhd
--
-- LOGIC CORE: DDR Data Path Module
-- MODULE NAME: ddr_data_path()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- R
www.eeworm.com/read/103567/15728930
vhd ddr_sdram_tb.vhd
--/******************************************************************************
--*
--* LOGIC CORE: SDR SDRAM Controller test bench
--* MODULE NAME: sdr_sdram_tb()
--*
www.eeworm.com/read/103567/15728936
vhd ddr_data_path.vhd
--
-- LOGIC CORE: DDR Data Path Module
-- MODULE NAME: ddr_data_path()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- R
www.eeworm.com/read/102471/15780247
vhd sdrm_timing_tb.vhd
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use std.textio.all;
library unisim;
use unisim.vcomponents.all;
USE work.ihdlutil.all;
USE work.vrlgutil.all;
USE std.textio.