poc.vhd

来自「基于VHDL的POC接口控制器,用于CPU与打印机间的数据控制」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity poc is
port(
clk,rdy:in std_logic;
d:in std_logic_vector(7 downto 0);
tr:out std_logic;
pd:out std_logic_vector(7 downto 0)
);
end poc;
architecture behave of poc is
signal br:std_logic_vector(7 downto 0);
signal sr7:std_logic;
begin
process(clk,rdy)
begin
if(clk'event and clk='1')then
if(rdy='0')then
sr7<='1';
br<=d;
end if;
if(rdy='1')then
sr7<='0';
pd<=br;
tr<='1';
end if;
end if;
end process;
end behave;