代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/248277/12586017
vhd mul3.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mul3 is
port(in1,in2,in3:std_logic_vector(7 downto 0);
sela,selb,selc:in std_logic;
dout:out std_logic_vector(7 downto 0)
);
e
www.eeworm.com/read/248277/12586047
vhd counter60.vhd
--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/248277/12586147
vhd counter60.vhd
--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/248277/12586154
vhd counter100.vhd
--counter100
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter100 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/248277/12586176
vhd counter60.vhd
--counter60
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter60 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/248277/12586190
vhd counter100.vhd
--counter100
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter100 is
port(clk,clr:in std_logic;
c:out std_logic;
www.eeworm.com/read/248277/12586546
vhd counter_1024.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_1024 is
port(clk,clr,en,updn,bcdwr:in std_logic;
datain:in std_logic_vector(9 downt
www.eeworm.com/read/334523/12596036
vhd fenlu.vhd
Library ieee; --输出选择模块
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity fenlu is
Port(clk,reset,set:in std_logic;
en:in
www.eeworm.com/read/334523/12596608
vhd year1.vhd
Library ieee; --年份模块
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity year1 is
Port(clky,set,reset:in std_logic;
y1,
www.eeworm.com/read/146918/12603040
vhd my_d.vhd
-- MAX+plus II VHDL
-- Clearable my_d
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY my_d IS
PORT
(
d,sd,rd : IN STD_LOGIC;
clk : IN STD_LOGIC;
q,nq : OUT STD_L