代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
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www.eeworm.com/read/415351/11075526
txt 莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/415351/11075544
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/415351/11075569
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/415351/11075593
txt 带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/415351/11075600
txt 莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/415351/11075616
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/269079/11109737
vhd counter.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTER IS
PORT
(CLK,CIN,BCD1WR,BCD10WR:IN STD_LOGIC;
DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
www.eeworm.com/read/268983/11112529
vhd sta.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity sta is
port (
clk:in STD_LOGIC;
dir:out std_logic_vector(2 downto 0);
divide:out STD_LOGIC
);
end sta;
architecture a o
www.eeworm.com/read/414309/11121267
vhd avr_core_comppack.vhd
--************************************************************************************************
-- Component declarations for AVR core
-- Version 1.52? (Special version for fhe JTAG OCD)
-- Desi
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vhd io_reg_file.vhd
--************************************************************************************************
-- Internal I/O registers (implemented inside the core) decoder/multiplexer
-- for AVR core
-- Ve